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ColdFire CF4e Core User’s Manual
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Local Memory Overview
Figure 8-1. Generic CF4e Block Diagram
The system buses have the following hierarchy:
K-Bus—Instruction and operand; processor core and dedicated on-chip memories
M-Bus—Internal multi-master with centralized arbitration
S-Bus—Slave module bus controlled by the system integration module (SIM)
E-Bus—External interface bus
To maximize processor performance, RAM, ROM, and cache controllers reside on the
high-speed local bus. These controllers support a range of memory sizes, such that when
coupled with the use of compiled memory arrays, provide system designers with the ability
to configure the implementation with the optimum amount of local memory for a given
application.
The KROM controllers are each associated with a ROMBAR control register (KROM0
with ROMBAR0 and KROM1with ROMBAR1). A CF4e design may have 0–2 KROM
controllers. The controllers independently support array sizes of 512 bytes, and 1, 2, 4, 8,
16 or 32 Kbytes. These arrays can be configured by a bit in the appropriate ROMBAR
control register to be on either the instruction K-Bus or the data K-Bus. This allows the
KROM controllers and their associated arrays to be moved from one K-Bus to the other.
Input configuration signals provide the ability to automatically load the ROMBAR control
registers at reset so the read-only memories can be used as boot devices.
Debug
E
K2M
ICACHE
Ctrl
KRAM0
Ctrl
KROM0
Ctrl
DCACHE
Ctrl
KRAM1
Ctrl
KRAM1
Ctrl
ICACHE
Tag/Data
Arrays
KRAM0
Mem
Array
KROM0
Mem
Array
ICACHE
Tag/Data
Arrays
KRAM1
Mem
Array
KROM1
Mem
Array
Slave
Module
Slave
Module
Master
Module
System
Integration
Module
S-Bus
M-Bus
E-Bus
CF4e
CPU
CF4e Core Kmem
CF4e Core
Instruction K-Bus
Data K-Bus
Data K-Bus
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