2-8
ColdFire CF4e Core User’s Manual
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Supervisor Programming Model
Figure 2-6. Supervisor Programming Model
2.3.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits.
Supervisor software can read or write the entire SR; user software can read or write only
SR[7–0], described in Section 2.2.5, “Condition Code Register (CCR).” Bits in the system
byte indicate processor states—trace mode (T), supervisor or user mode (S), and master or
interrupt state (M). SR is set to 0x27
xx
after reset.
Table 2-2 describes SR fields.
15
0
(CCR)
SR
31
19
Status register
OTHER_A7 Supervisor A7 stack pointer
VBR
Vector base register
CACR
Cache control register
ASID
Address space ID register
ACR0
Access control register 0 (data)
ACR1
Access control register 1 (data)
ACR2
Access control register 2 (instruction)
ACR3
Access control register 3 (instruction)
MMUBAR
MMU base address register
ROMBAR0 ROM base address register 0
ROMBAR1 ROM base address register 1
RAMBAR0
RAM base address register0
RAMBAR1
RAM base address register 1
MBAR
Module base address register (not a core register)
Must be zeros
15
14
13
12
12
10
8
7
5
4
3
2
1
0
System byte
Condition code register (CCR)
Field
T
—
S
M
—
I
—
X
N
Z
V
C
Reset
0
0
1
0
0
111
000
—
—
—
—
—
R/W R/W
R
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
Figure 2-7. Status Register (SR)
Table 2-2. Status Field Descriptions
Bits
Name
Description
15
T
Trace enable. When T is set, the processor performs a trace exception after every instruction.
13
S
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
F
Freescale Semiconductor, Inc.
n
.