
Chapter 9. Core Interface
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9-13
ColdFire Master Bus
A bus cycle is a request to transfer data between the bus master and a slave device. To
ensure that master and slave devices can handle misaligned operands, the bus architecture
must guarantee that each data byte is aligned to the proper lane. For line transfers, data
alignment is treated as 4 longword transfers. The next section discusses protocols to handle
these transfers. M-Bus transfers assume 32-bit M-Bus devices. The SIM generally handles
dynamic sizing to byte or word ports; to support this, M-Bus masters must perform some
data replication functions during write cycles. For all transfers, maddr[31:2] is the
longword base address of the first byte of the reference item. maddr[1:0] indicates the byte
offset from this address. msiz[1:0] and the 2 low-order address bits determine data bus
usage. Table 9-4 shows mrdata requirements for read transfers.
Table 9-5 shows mwdata requirements for write transfers.
Table 9-4 and Table 9-5 define all allowable msiz[1:0] and maddr[1:0] combinations.
9.3.2.5 Line Transfers
A line is defined as being 16 bytes wide, aligned in memory on 0-modulo-16 address
boundary. On the M-Bus, this is seen as an address phase followed by a data phase during
which 4 longwords of data are transferred a longword per transfer. Although the line is
Table 9-4. mrdata Requirements for Read Transfers
Size
msiz[1:0]
maddr[1:0]
mrdata[31:24]
mrdata[23:16]
mrdata[15:8]
mrdata[7:0]
Byte
01
00
OP3
Ignored
Ignored
Ignored
01
01
Ignored
OP3
Ignored
Ignored
01
10
Ignored
Ignored
OP3
Ignored
01
11
Ignored
Ignored
Ignored
OP3
Word
10
00
OP2
OP3
Ignored
Ignored
10
10
Ignored
Ignored
OP2
OP3
Long
00
00
OP0
OP1
OP2
OP3
Line
11
00
OP0
OP1
OP2
OP3
Table 9-5. mwdata Bus Requirements for Write Transfers
Size
msiz[1:0]
maddr[1:0]
mwdata[31:24]
mwdata[23:16]
mwdata[15:8]
mwdata[7:0]
Byte
01
00
OP3
Ignored
Ignored
Ignored
01
01
OP3
OP3
Ignored
Ignored
01
10
OP3
Ignored
OP3
Ignored
01
11
OP3
Ignored
Ignored
OP3
Word
10
00
OP2
OP3
Ignored
Ignored
10
10
OP2
OP3
OP2
OP3
Long
00
00
OP0
OP1
OP2
OP3
Line
11
00
OP0
OP1
OP2
OP3
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