Chapter 8. Local Memory
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8-11
Local Memory Connection Specification
The KROM controllers support an array width of 32 bits and array sizes of 512 bytes and
1, 2, 4, 8, 16, 32, and 64 Kbytes. The controller uses the krom{0,1}size[3:0] inputs to
determine the connected array size as shown in Table 8-6.
The signals in Table 8-7 connect a KRAM controller to its ROM array.
KROM memories are 32 bits wide. The krom0do[31:0] and krom1do[31:0] signals are the
array output data for all sizes of KRAM0 and KRAM1.
The krom0addr[15:2] and krom1addr[15:2] signals are the array addresses. Each KROM
controller provides enough address bits for the largest supported array sizes.
The 2 low-order address bits, which are not sourced from the KROM controller to the
KROM arrays directly, select the bytes within the 32-bit KROM data array interface. For
read operations, the KROM controller always fetches 32 bits and sends this information to
the 32-bit K-Bus. The K-Bus data requester is responsible for using only the bytes selected.
The array address is connected as shown in Table 8-8 for all supported KROM array sizes.
Table 8-6. KRAM0/KRAM1 Size
krom{0,1}size[3:0]
Total Size
Configuration
0000
0 bytes
KROM{0,1} disabled
0001
512 bytes
128 x 4 bytes
0010
1 Kbytes
256 X 4 bytes
0011
2 Kbytes
512 X 4 bytes
0100
4 Kbytes
1024 X 4 bytes
0101
8 Kbytes
2048 X 4 bytes
0110
16 Kbytes
4096 X 4 bytes
0111
32 Kbytes
8192 X 4 bytes
1000
64 Kbytes
16384 X 4 bytes
1001–1111
RFU
RFU
Table 8-7. KROM{0,1} Memory Array Connections
Direction/Size
Signal Name
Definition
output[15:2]
krom0addr
krom1addr
KROM0 15 bit address
KROM1 15 bit address
output
krom0csb
krom1csb
KROM0 chip select (active-low)
KROM1 chip select (active-low)
input[31:0]
krom0do
krom1do
KROM0 32 bit data out
KROM1 32 bit data out
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