6-16
ColdFire CF4e Core User’s Manual
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Operand Execution Pipeline (OEP)
Figure 6-5. for_loop Example
6.3.6 Operand Memory Sequence-Related Stalls
Operand reads and writes occur in different OEP stages; operand reads occur in OC1 and
operand writes occur in ST. Accordingly, the read-after-write hazard in a given local
memory can cause a 1-cycle stall. Specifically, if a memory read occupies OC1 and an
operand write is in ST, the read stalls for a cycle to allow the write to complete because the
memory array can only perform one operation per cycle. Performance measurements on
this type of stall show a relatively minor degradation factor of 0.04 cycles per instruction.
NOTE:
Read and write accesses must both be to the same local
memory. For example, both access the data cache.
6.3.7 V4 OEP Summary
Measurements across the entire embedded suite into an ideal, infinitely large local memory
show base CPI metrics ranging from 0.75 to 2.16 cycles per instruction, where the larger
number includes benchmarks with significant use of multi-cycle arithmetic operations such
as integer multiply and divide. The geometric mean across the entire suite is 1.34 cycles per
instruction for the V4 core. Section 6.5, “Instruction Execution Times,” lists instruction
execution times. Figure 6-6 shows a block diagram of the Ex execute engines of the V4
OEP.
Register elements in Figure 6-6 are shown as boxes with double lines showing boundaries
between pipeline stages. Data multiplexers where various source operands are connected at
the top are shown as ellipses; selected data is shown on the bottom.
fmov
fmul
fmul
fmul
fadd
fadd
fadd
fadd
fmov
fmov
OEP DS
OEP OAG
OEP OC1
OEP OC2
OEP EX
Cycle
FPU EX1
FPU EX2
FPU EX3
FPU EX4
fmul
fadd
subq subq subq subq
lea
fmov fmov fmov
fmov
fmul
fadd
fadd
fadd
fadd
subq
lea
fmov fmov fmov
1
2
3
4
5
6
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8
9
10
0
fmov fmul
fadd
subq
lea
fmov fmov
fmov
fmul
fadd
subq
lea
fmov fmov
fmov
fmul
fadd
subq
lea
fmov
fmov
fmul
fmov
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Freescale Semiconductor, Inc.
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