11-22
ColdFire CF4e Core User’s Manual
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Programming Model
conditions. Breakpoint logic may be configured as one- or two-level triggers. TDR[31–16]
or XTDR[31–16] define second-level triggers and bits 15–0 define first-level triggers.
NOTE:
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR and XTDR (by clearing
TDR[29,13] and XTDR[29,13]) before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Table 11-18 describes TDR fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
TRC
EBL
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
DI
EAI
EAR
EAL
EPC
PCI
Reset
All zeros
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the
WDMREG
command.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
—
EBL
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
DI
EAI
EAR
EAL
EPC
PCI
Reset
All zeros
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the
WDMREG
command.
DRc[4–0]
0x07
Figure 11-13. Trigger Definition Register (TDR)
Table 11-18. TDR Field Descriptions
Bits
Name
Description
31–30
TRC
Trigger response control. Determines how the processor responds to a completed trigger condition.
The trigger response is always displayed on PSTDDATA.
00 Display on PSTDDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
15–14
—
Reserved, should be cleared.
29/13
EBL
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger. If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are
disabled.
Second-Level Triggers
First-Level Triggers
F
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n
.