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型號(hào): V4ECFUM
英文描述: ColdFire CF4e Core User's Manual
中文描述: 核心的ColdFire CF4e用戶手冊(cè)
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Chapter 11. Debug Support
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11-7
Real-Time Trace Support
Table 11-4 shows the encoding of these signals.
Table 11-4. Processor Status Encoding
PST[3:0]
Definition
Hex
Binary
0x0
0000
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
clock cycles, subsequent clock cycles are indicated by driving PSTDDATA outputs with this encoding.
0x1
0001
Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle of
an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
0x2
0010
Begin execution of two instructions. For superscalar instruction dispatches, this encoding signals the
first clock cycle of the simultaneous instructions’ execution.
0x3
0011
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode. If the display of the ASID is enabled (CSR[3] = 1), the following occurs:
The 8-bit ASID follows the instruction address; that is, the PSTDDATA sequence is {0x3, 0x5,
marker, instruction address, 0x8, ASID}, where 0x8 is the ASID data marker.
Whenever the current ASID is loaded by the privileged MOVEC instruction, the ASID is displayed
on PSTDDATA. The resulting PSTDDATA sequence for the MOVEC instruction is then {0x1, 0x8,
ASID}, where the 0x8 is the data marker for the ASID.
0x4
0100
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to
the PSTDDATA port, independent of debug module configuration. When WDDATA is executed, a value
of 0x4 is signaled, followed by the appropriate marker, and then the data transfer on the PSTDDATA
port. Transfer length depends on the WDDATA operand size.
0x5
0101
Begin execution of taken branch or SYNC_PC command. For some opcodes, a branch target address
may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins
the data output. See Section 11.3.1, “Begin Execution of Taken Branch (PST = 0x5).” Also indicates
that the SYNC_PC command has been issued.
0x6
0110
Begin execution of instruction plus a taken branch. The processor completes execution of a taken
conditional branch instruction and simultaneously starts executing the target instruction. This is
achieved through branch folding.
0x7
0111
Begin execution of return from exception (RTE) instruction.
0x8–
0xB
1000–
1011
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The
value is driven onto the PSTDDATA port one cycle before the data is displayed.
0x8 Begin 1-byte transfer on PSTDDATA.
0x9 Begin 2-byte transfer on PSTDDATA.
0xA Begin 3-byte transfer on PSTDDATA.
0xB Begin 4-byte transfer on PSTDDATA.
0xC
1100
Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally
trace) generate a different encoding, as described below. Because the 0xC encoding defines a
multiple-cycle mode, PSTDDATA outputs are driven with 0xC until exception processing completes.
0xD
1101
Emulator mode exception processing.
Displayed during emulation mode (debug interrupt or optionally
trace). Because this encoding defines a multiple-cycle mode, PSTDDATA outputs are driven with 0xD
until exception processing completes.
0xE
1110
A breakpoint state change causes this encoding to assert for one cycle only followed by the trigger
status value. If the processor stops waiting for an interrupt, the encoding is asserted for multiple cycles.
See Section 11.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).”
0xF
1111
Processor is halted. Because this encoding defines a multiple-cycle mode, the PSTDDATA outputs
display 0xF until the processor is restarted or reset. (see Section 11.5.1, “CPU Halt”)
F
Freescale Semiconductor, Inc.
n
.
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