
INDEX
Index
Index-5
WDMREG, 11-54
write control, 11-52
write debug module, 11-54
XTDR, 11-23
ROM
base address registers, 8-29
initialization, 8-31
operation, 8-28
overview, 8-28
programming model, 8-29
ROMBAR power management programming, 8-32
S
SRAM
initialization, 8-25
initialization code, 8-26
operation, 8-23
overview, 8-22
programming model, 8-23
Stalls
EMAC-specifis, 6-13
OEP, 6-11, 6-16
Status register, 2-8
STOP instruction, 11-9, 11-28
Supervisor programming model, 2-7
Supervisor/user stack pointers, 2-9
System bus controller, 8-18
T
Test controller
MTMOD encodings, 12-32
Test features
CF4e core
inputs, 12-8
outputs, 12-11
noncore
inputs, 12-13
outputs, 12-15
scan chains
block diagram, 12-3
core, 12-2
general, 12-2
wrapper, 12-2
timing, 12-8
wrapper
block diagram, 12-7
cells, 12-5
general, 12-3
Timing
branch instruction execution, 6-28
core interface characteristics, 13-1
MOVE instructions, 6-23
one-operand, 6-24
two-operand, 6-25
Transfers, line, 9-13
V
V4
basic pipeline strategy, 6-1
OEP
conceptual model, 6-6
summary, 6-16
programming model, 1-5
Variant address, 11-8
Vector base register, 2-9, 2-9, 7-2
Virtual memory
access error stack frame additions, 10-8
architecture processor support, 10-7
management architecture, 10-1
precise faults, 10-8
supervisor/user stack pointers, 10-8
W
WDDATA execution, 11-7
F
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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