Chapter 12. Test
12-21
BIST
controller to indicate when memories are in a hold state.
As soon as all of the memories are held in the first group, the second group is initialized.
This staging is controlled internally and does not affect the user. Staging adds 200 ms to the
BIST memory testing and an additional 200 ms to data retention testing if it is not included
in memory testing. Staging increases estimated test time from 0.9 to 1.3 seconds.
12.3.5 Testing Algorithms
Data and instruction cache arrays are tested along with the RAM arrays using the March C+
algorithm. ROM arrays are tested using a prime polynomial of order 32.
12.3.5.1 March C+ Algorithm
The March C+ algorithm has six parts with an example background of 5s and As.
NOTE:
Automatic holds, or self pauses, occur only during background
5-A at the end of the first two parts.
1. Part 1
a) Begin at first address location (address 0)
b) Initialize (write) all locations with the initial data background
c) Conduct self-pause (only for first data background pass 5-A)
2. Part 2
a) Release self-pause (only for first data background pass 5-A)
b) Begin at first address location (address 0)
c) Read (initial)—write (complement)—read (complement)
d) Increment address and repeat for entire address space
e) Conduct self-pause (only for first data background pass 5-A)
3. Part 3
a) Release self-pause (only for first data background pass 5-A)
b) Begin at first address location (address 0)
c) Read (data)—write (complement)—read (complement)
d) Increment address and repeat for entire address space
4. Part 4
a) Begin at last address location (address max)
b) Read (data)—write (complement)—read (complement)
c) Decrement address and repeat for entire address space
F
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