CONTENTS
Paragraph
Number
Title
Page
Number
Contents
ix
8.6.2
8.6.2.1
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.7.2.1
8.7.2.2
8.7.3
8.7.4
8.7.4.1
8.7.4.2
8.7.4.3
8.7.5
8.7.6
8.7.6.1
8.7.6.2
8.7.6.3
8.7.6.4
8.7.7
8.7.8
8.7.8.1
8.7.8.2
8.7.8.2.1
8.7.8.2.2
8.7.9
8.7.10
8.7.10.1
8.7.10.2
8.7.11
8.7.12
8.7.13
8.7.13.1
ROM Programming Model........................................................................... 8-29
ROM Base Address Registers (ROMBAR0/ROMBAR1)....................... 8-29
ROM Initialization........................................................................................ 8-31
Programming ROMBARs for Power Management...................................... 8-32
Cache Overview................................................................................................ 8-32
Optimizing Cache Recommendation............................................................ 8-33
Cache Organization....................................................................................... 8-33
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified....... 8-34
Cache at Start-Up...................................................................................... 8-34
Cache Operation ........................................................................................... 8-35
Caching Modes............................................................................................. 8-38
Cacheable Accesses.................................................................................. 8-39
Write-Through Mode (Data Cache Only)................................................. 8-39
Copyback Mode (Data Cache Only)......................................................... 8-39
Cache-Inhibited Accesses............................................................................. 8-39
Cache Protocol.............................................................................................. 8-40
Read Miss ................................................................................................. 8-41
Write Miss (Data Cache Only)................................................................. 8-41
Read Hit.................................................................................................... 8-41
Write Hit (Data Cache Only).................................................................... 8-42
Cache Coherency (Data Cache Only)........................................................... 8-42
Memory Accesses for Cache Maintenance................................................... 8-42
Cache Filling............................................................................................. 8-42
Cache Pushes............................................................................................ 8-42
Push and Store Buffers......................................................................... 8-43
Push and Store Buffer Bus Operation................................................... 8-43
Cache Locking.............................................................................................. 8-44
Cache Registers............................................................................................. 8-45
Cache Control Register (CACR).............................................................. 8-46
Access Control Registers (ACR0–ACR3)................................................ 8-48
Cache Management....................................................................................... 8-50
Cache Operation Summary........................................................................... 8-52
Instruction Cache State Transitions.............................................................. 8-52
Data Cache State Transitions.................................................................... 8-53
Chapter 9
Core Interface
9.1
9.2
9.3
9.3.1
Core Interface Signals......................................................................................... 9-1
CF4e Pin Characteristics..................................................................................... 9-2
ColdFire Master Bus........................................................................................... 9-6
M-Bus Signals................................................................................................. 9-6
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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