Agere Systems Inc.
111
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
11 Minibridge
(continued)
5-9412 (F)
Figure 33. Minibridge Read/Write Access Cycles
Notes:
n
Strobes are created based on the T8110 internal 65.536 MHz clock. MB_CS, MB_RD, and MB_WR are shown
here as active-low, but may be programmed active-high via the CS strobe inversion and RD-WR strobe inversion
registers.
n
User-programmable wait-states are allowed at five points for either read or write cycles:
— Delay from valid address to MB_CSn assertion (address wait).
— Delay from MB_CSn assertion to the leading edge of the MB_RD (or MB_WR) strobe (setup wait).
— Pulse width of the MB_RD (or MB_WR) strobe (width wait).
— Delay from MB_RD (or MB_WR) trailing edge to the deassertion of MB_CSn (hold wait).
— Delay from deassertion of MB_CSn to address invalid (address wait).
n
With no wait-states, the minimum access time (read or write) for the minibridge interface is 76.3 ns
(five 65.536 MHz clock cycles).
Notes:
n
Timing protocol. Any user-programmable wait-states are defined in increments of 65.536 MHz clock periods
(15.25 ns):
— taccess: total access time. Minimum = 76.3 ns (five clock cycles), maximum = 19.5
μ
s (accumulation of user-
programmed wait-states).
— tasu: address setup to MB_CSn active. Minimum = 15.25 ns (one clock cycle), maximum = 3.9
μ
s
(256 clock cycles) user-programmable via CSn address wait register.
— tah: address hold from MB_CSn inactive. Minimum = 15.25 ns (one clock cycle), maximum = 3.9
μ
s
(256 clock cycles) user-programmable via CSn address wait register.
— trdsuwait: delay from MB_CSn active to leading edge of MB_RD strobe. Minimum = 15.25 ns (one clock
cycle), maximum = 3.9
μ
s (256 clock cycles) user-programmable via CSn RD setup wait register.
ADDRESS VALID
WRITE DATA VALID
RD DATA
VALID
taccess
trdsuwait
trdholdwait
trdh
twrwidth
twrsuwait
twrholdwait
tasu
trdwidth
tah
twrsu
trdsu
T8110
INTERNAL CLOCK
(65.538 MHz)
MB_A[15:0]
MB_CSn
MB_D[15:0]
(READ CYCLE)
MB_WR
MB_D[15:0]
(WRITE CYCLE)
MB_RD