
Agere Systems Inc.
177
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
17 JTAG/Boundary Scan
17.1 The Principle of Boundary-Scan Architecture
Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a
boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are
referred to as output cells. Input and output is relative to the core logic of the device.
At any time, only one register can be connected from TDI to TDO. For example, instruction register (IR), bypass,
boundary-scan, ident, or even some appropriate register internal to the core logic (see Figure 65). The selected
register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as
EXTEST (boundary-scan register selected), whereas others are optional, such as the IDCODE nstruction (Ident
register selected).
Figure 65. IEEE* 1149.1 Boundary-Scan Architecture
Figure 65 shows the following elements:
n
A set of four dedicated test pins, test data in (TDI), test mode select (TMS), test clock (TCK), test data out
(TDO), and one optional test pin test reset (TRSTN). These pins are collectively referred to as the test access
port (TAP).
n
A boundary-scan cell on each device’s primary input and primary output pin, connected internally to form a serial
boundary-scan register (boundary scan).
n
A finite-state machine TAP controller with inputs TCK and TMS.
n
An n-bit (n = 3) instruction register (IR), holding the current instruction.
n
A 1-bit bypass register (BYPASS).
n
An optional 32-bit identification register (ident) capable of being loaded with a permanent device identification
code.
* IEEEis a registered trademark of The Institute of Electrical and Electronic Engineers, Inc.
INTERNAL
CORE LOGIC
IDENTIFICATION REGISTER
INSTRUCTION REGISTER (IR)
TEST MODE SELECT
TEST CLOCK
TMS
TCK
TEST RESET (TRSTN)
TEST DATA OUT
TDO
TDI
TEST DATA IN
BYPASS
TAP
CONTROLLER