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參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 163/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
161
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
14
Connection Control—Standard and Virtual Channel
(continued)
For a virtual channel in the
push
direction, the T8110 fills its internal buffer with incoming TDM serial stream data.
Once the internal buffer for that channel is full, the T8110 initiates a burst transfer of that data to the external buffer.
For a virtual channel in the
pull
direction, the T8110 empties its internal buffer to outgoing TDM serial stream data.
Once the internal buffer for that channel is empty, the T8110 initiates a burst transfer to fetch more data from the
external buffer.
14.2.3.4.2 Descriptor Table
The first portion of a T8110-initiated transfer is to fetch control information associated with a particular virtual chan-
nel. The third portion is an update of that control information, with the transfer of data to/from the external buffer in
between; see Section 4.2.2 on page 32 and to Figure 13 on page 33. The control information is stored in a descrip-
tor table, which exists in the PCI bus address space and is accessible by both the T8110 and the
USER
. The
T8110 must have access to the descriptor table’s base address, which must be loaded into T8110 registers
0x00110—113 prior to any virtual channel activity. There is one entry in the descriptor table for each of the possible
512 virtual channels. Each entry consists of 8 bytes (2 DWORDS). The maximum space required for the descriptor
table is (512 * 8) = 4 Kbytes. A descriptor table entry contains the following information.
n
External buffer base address. This is the base address where the external buffer space for this particular virtual
channel begins. Note that only bits [31:12] are defined, which means the external buffer space for a virtual chan-
nel is addressed on 4 Kbyte boundaries in the PCI space. This region is read-only for T8110, read-write for the
USER
.
n
External buffer last address. This is the last address offset in the external buffer space for this particular virtual
channel (DWORD-aligned). This region is read-only for T8110, read-write for the
USER
.
n
Control flags. All flags are read-only for T8110, read-write for the
USER
:
— SE, stop enable. This determines whether the external buffer is treated as circular for this virtual channel
(refer to Section 14.2.3.4.4). 0 = buffer is circular (T8110 can roll over at end-of-buffer), 1 = the buffer is not
circular (T8110 must stop at end of buffer).
— OE, overwrite enable. This determines whether the T8110 can overwrite unread data in the external buffer for
this virtual channel (refer to Section 14.2.3.4.4). 0 = overwrite is disabled, 1 = overwrite is enabled.
— L, lock. This determines whether the T8110 is allowed access to the external buffer for this virtual channel.
0 = not locked, 1 = locked.
n
UF. Toggled by the
USER
whenever the UOR pointer rolls over at the end of the external buffer. Read-only for
the T8110.
n
UOR. This is a
USER
-updated offset pointer within the defined 4K external buffer space for this virtual channel.
Read-only for the T8110.
n
GBS (status). This is supplemental information on the status of the external buffer for this virtual channel (refer to
Section 14.2.3.4.4). These flags are read-write for both the T8110 and the
USER
. Refer to Table 116.
n
TF. Toggled by the T8110 whenever the TOR pointer rolls over at the end of the external buffer. Read-write for
both the T8110 and the
USER
.
n
TOR. T8110 updated offset pointer within the defined 4K external buffer space for this virtual channel. Read-
write for both the T8110 and the
USER
.
Table 115. Descriptor Table
DWORD
First
DWORD
Second DWORD
Bits[31:24]
Bits[23:16]
Bits[15:8]
Bits[7:0]
External buffer base address
UOR[11:0]
External buffer last address
TOR[11:0]
S
E
O
E
L
U
F
GBS
[2:0]
T
F
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