Agere Systems Inc.
115
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
12 Error Reporting and Interrupt Control
(continued)
12.1.2 Interrupts Via External GP[7:0]
12.1.2.1 GPIO Interrupt Pending Register
The GPIO interrupt pending register stores detected interrupts via the GP[7:0] signals. The user can clear specific
pending bits by writing 1 to that bit (write-1-to-clear). Interrupts via these signals are maskable via the GPIO inter-
rupt enable register.
Table 90. GPIO Interrupt Pending Register
Byte
Address
0x00604
Name
Bit(s) Mnemonic
Value
Function
GPIO Interrupt Pending
7
JG7OB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No pending interrupts via GP7 (default).
Pending interrupt via GP7.
No pending interrupts via GP6 (default).
Pending interrupt via GP6.
No pending interrupts via GP5 (default).
Pending interrupt via GP5.
No pending interrupts via GP4 (default).
Pending interrupt via GP4.
No pending interrupts via GP3 (default).
Pending interrupt via GP3.
No pending interrupts via GP2 (default).
Pending interrupt via GP2.
No pending interrupts via GP1 (default).
Pending interrupt via GP1.
No pending interrupts via GP0 (default).
Pending interrupt via GP0.
Disable (mask) interrupts via GP7 (default).
Enable (unmask) interrupts via GP7.
Disable (mask) interrupts via GP6 (default).
Enable (unmask) interrupts via GP6.
Disable (mask) interrupts via GP5 (default).
Enable (unmask) interrupts via GP5.
Disable (mask) interrupts via GP4 (default).
Enable (unmask) interrupts via GP4.
Disable (mask) interrupts via GP3 (default).
Enable (unmask) interrupts via GP3.
Disable (mask) interrupts via GP2 (default).
Enable (unmask) interrupts via GP2.
Disable (mask) interrupts via GP1 (default).
Enable (unmask) interrupts via GP1.
Disable (mask) interrupts via GP0 (default).
Enable (unmask) interrupts via GP0.
6
JG6OB
5
JG5OB
4
JG4OB
3
JG3OB
2
JG2OB
1
JG1OB
0
JG0OB
0x00605
GPIO Interrupt Enable
7
JG7EB
6
JG6EB
5
JG5EB
4
JG4EB
3
JG3EB
2
JG2EB
1
JG1EB
0
JG0EB