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參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 192/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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190
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix A. Constant and Minimum Delay Connections
A.1 Connection Definitions
A forward connection is defined as one in which the output
to
time slot has a greater value than the input
from
time-slot, or, put another way, the delta between them is positive.
A reverse connection is defined as one in which the output
to
time slot has a lesser value than the input
from
time
slot, and the delta between them is negative.
For example, going from TS(1) to TS(38) is a forward connection, and the TS
is +37, but going from TS(38) to
TS(1) is a reverse connection, with a TS
of
–37:
where TS
= TS(
to
) – TS(
from
).
Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later):
STR
= STR(
to
) – STR(
from
).
There is only one combination which forms a TS
of +127 or –127:
TS
= TS(127) – TS(0) = +127, and
TS
= TS(0) – TS(127) = –127,
but there are two combinations which form TS
s of +126 or –126:
TS
= TS(127) – TS(1) = TS(126) – TS(0) = +126, and
TS
= TS(1) – TS(127) = TS(0) – TS(126) = –126,
there are three combinations which yield +125 or –125, and so on.
The user can utilize the TS
to control the latency of the resulting connection. In some cases, the latency must be
minimized. In other cases, such as a block of connections which must maintain some relative integrity while cross-
ing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time-slots)
to maintain the integrity of this virtual frame.
The device uses a control bit at each connection memory location, VFC, for controlling latency, allowing each con-
nection to select one of two alternating data buffers.
A.2 Delay Type Definitions
Constant Delay
—This is a well-defined, predictable, and linear region of latency in which the
to
time slot is at least
128 time slots after the
from
time-slot, but no more than 256 time slots after the
from
time-slot.
Mathematically, constant delay latency is described as follows*, with L denoting latency, and VFC set to the value
indicated:
Forward connections, VFC = 1: L = 128 + TS
(0
≤
TS
≤
127)
Reverse connections, VFC = 0: L = 256 + TS
(–127
≤
TS
≤
0)
Example:
Switching from TS(37) to TS(1) as a constant delay, the delta is –36, so FME is set to 0 and the result-
ing latency is 256 – 36 = 220 time slots. Thus, the connection will be made from TS(37) of frame(n) to
TS(1) of frame(n + 2).
Simple summary:
Use constant delay for latencies of 128 to 256 time slots,
set VFC = 1 for forward connections,
set VFC = 0 for reverse connections.
* Since TS
= TS(
to
) –TS(
from
), the user can modify the equations to solve for either TS(
to
) or TS(
from
).
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