82
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
7 Clock Architecture
(continued)
7.7 Clock Circuit Operation
—Fallback and Failsafe
Fallback is a means to alter the reference source to APLL1 by switching between two clock control register sets
upon detection of a fallback event. Failsafe is a feature to provide a safety net for the reference source to APLL1,
independent of clock fallback.
7.7.1 Clock Fallback
Clock fallback is a means to alter the APLL1 reference clock source upon detection of a fallback event and is con-
trolled by eight registers, 0x00108—0x0010F (refer to Section 6.1.4 on page 49). These registers enable and con-
trol the state transitions that determine which of two clock register sets is used to control the APLL1 reference clock
source (see Section 7.1 on page 63 through Section 7.3, Table 64 on page 85, and Figure 23 on page 84).
7.7.1.1 Fallback Events
Clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (reg-
ister 0x00109, lower nibble) and a fallback event occurs. When enabled, there are three ways to trigger the fallback
event:
n
Software, via a FORCE_FALLBACK command. The user sets bit 2 of the fallback control register, 0x00108, cre-
ating a software-invoked fallback event.
n
Hardware via the fallback trigger enable registers, 0x0010A—0x0010B. User may enable specific watchdog tim-
ers and corresponding fallback trigger enable bits. If a watchdog timer indicates a clock error, and its correspond-
ing trigger enable bit is set, a hardware-invoked fallback event is produced.
n
Hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. The legacy modes are
included to maintain backwards compatibility with earlier
Ambassador
devices. User may enable specific watch-
dog timers, but the fallback trigger enable registers are ignored. Instead, the watchdogs which are allowed to
trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200
(refer to Table 63). If a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via
the main input selector, a hardware-invoked fallback event is produced.