
216
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
JSEOB
JSFOB
JS0EB
JS1EB
JS2EB
JS3EB
JS4EB
JS5EB
JS6EB
JS7EB
JS8EB
JS9EB
JSAEB
JSBEB
JSCEB
JSDEB
JSEEB
JSFEB
JC0OB
JC1OB
JC2OB
JC3OB
JC4OB
JC5OB
JC6OB
JC7OB
JC8OB
JC9OB
JCAOB
JCBOB
JCCOB
JCDOB
JCEOB
JCFOB
JC0EB
JC1EB
JC2EB
JC3EB
JC4EB
JC5EB
JC6EB
Interrupt pending SYSERR E
Interrupt pending SYSERR F
Interrupt from SYSERR 0
Interrupt from SYSERR 1
Interrupt from SYSERR 2
Interrupt from SYSERR 3
Interrupt from SYSERR 4
Interrupt from SYSERR 5
Interrupt from SYSERR 6
Interrupt from SYSERR 7
Interrupt from SYSERR 8
Interrupt from SYSERR 9
Interrupt from SYSERR A
Interrupt from SYSERR B
Interrupt from SYSERR C
Interrupt from SYSERR D
Interrupt from SYSERR E
Interrupt from SYSERR F
Interrupt pending CLKERR 0
Interrupt pending CLKERR 1
Interrupt pending CLKERR 2
Interrupt pending CLKERR 4
Interrupt pending CLKERR 5
Interrupt pending CLKERR 6
Interrupt pending CLKERR 7
Interrupt pending CLKERR 8
Interrupt pending CLKERR 9
Interrupt pending CLKERR A
Interrupt pending CLKERR B
Interrupt pending CLKERR C
Interrupt pending CLKERR D
Interrupt pending CLKERR E
Interrupt pending CLKERR F
Interrupt from CLKERR 0
Interrupt from CLKERR 1
Interrupt from CLKERR 2
Interrupt from CLKERR 3
Interrupt from CLKERR 4
Interrupt from CLKERR 5
Interrupt from CLKERR 6
Output
Output
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Enable
Enable
Enable
Enable
Enable
Enable
Enable
0x00609
0x00609
0x0060A
0x0060A
0x0060A
0x0060A
0x0060A
0x0060A
0x0060A
0x0060A
0x0060B
0x0060B
0x0060B
0x0060B
0x0060B
0x0060B
0x0060B
0x0060B
0x0060C
0x0060C
0x0060C
0x0060C
0x0060C
0x0060C
0x0060C
0x0060C
0x0060D
0x0060D
0x0060D
0x0060D
0x0060D
0x0060D
0x0060D
0x0060D
0x0060E
0x0060E
0x0060E
0x0060E
0x0060E
0x0060E
0x0060E
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Table 134. Mnemonic Summary, Sorted by Register
(continued)
Mnemonic
Description
Type
Register
Bit Position