
Agere Systems Inc.
117
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
12 Error Reporting and Interrupt Control
(continued)
12.1.4 System Interrupt Pending High/Low Registers
The system interrupt pending high/low registers store detected interrupts via the internal system error signals (refer
to Section 6.2.5 on page 59). The user can clear specific bits by writing 1 to that bit (write-1-to-clear).
Table 93. System Interrupt Pending High/Low Registers
Byte
Address
0x00608 System Interrupt Pending Low
Name
Bit(s) Mnemonic Value
Function
7
JS7OB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No pending interrupts via SYS7 (default).
Pending interrupt via SYS7.
No pending interrupts via SYS6 (default).
Pending interrupt via SYS6.
No pending interrupts via SYS5 (default).
Pending interrupt via SYS5.
No pending interrupts via SYS4 (default).
Pending interrupt via SYS4.
No pending interrupts via SYS3 (default).
Pending interrupt via SYS3.
No pending interrupts via SYS2 (default).
Pending interrupt via SYS2.
No pending interrupts via SYS1 (default).
Pending interrupt via SYS1.
No pending interrupts via SYS0 (default).
Pending interrupt via SYS0.
No pending interrupts via SYS15 (default).
Pending interrupt via SYS15.
No pending interrupts via SYS14 (default).
Pending interrupt via SYS14.
No pending interrupts via SYS13 (default).
Pending interrupt via SYS13.
No pending interrupts via SYS12 (default).
Pending interrupt via SYS12.
No pending interrupts via SYS11 (default).
Pending interrupt via SYS11.
No pending interrupts via SYS10 (default).
Pending interrupt via SYS10.
No pending interrupts via SYS9 (default).
Pending interrupt via SYS9.
No pending interrupts via SYS8 (default).
Pending interrupt via SYS8.
6
JS6OB
5
JS5OB
4
JS4OB
3
JS3OB
2
JS2OB
1
JS1OB
0
JS0OB
0x00609 System Interrupt Pending
High
7
JSFOB
6
JSEOB
5
JSDOB
4
JSCOB
3
JSBOB
2
JSAOB
1
JS9OB
0
JS8OB