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參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 33/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
31
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
(continued)
4.1.6.1 Posted Write Transaction
Only one posted write to the minibridge port may be queued at a time; please refer to Figure 6. The user
must
monitor a status bit (register status 8, bit 2) to determine whether a posted write is already queued before attempt-
ing more writes. Subsequent posted write attempts to the minibridge port while a queued posted write has not
completed result in an error condition. The queued write is allowed to complete, but the subsequent write is
ignored. Error is reported at register status 7, bit 2 (refer to Section 6.2.5 on page 59). Subsequent read attempts
from the minibridge port, while a posted write is queued, result in a target retry (refer to Figure 10).
4.1.6.2 Delayed Read Transaction
Only one delayed read from the minibridge port may be queued at a time. A delayed read transaction latches the
address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries
the same transaction
or
attempts a different read transaction from the minibridge port prior to the queued delayed
read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same
transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; refer to
Figure 8). Any subsequent posted write attempts to the minibridge port while a delayed read is in progress result in
an error condition. The delayed read is allowed to complete, but the write request is ignored. Error is reported at
register status 7, bit 2 (refer to Section 6.2.5 on page 59).
4.2 Initiator
The T8110 can initiate PCI transactions in order to perform packet payload switching between the local PCI bus
and the 64 H-bus/L-bus data streams. The T8110 initiates accesses in order to either send (or push) data received
from H-bus/L-bus streams to an external data buffer, or to retrieve (or pull) data from an external data buffer to
transmit out to the H-bus/L-bus streams. Each operation requires three PCI burst accesses. An external descriptor
table provides current read/write pointer status to the external data buffer. The T8110 fetches pointer information
from the descriptor table, transfers data to/from the external data buffer, and then updates the descriptor table
pointer information. For more details, see Section 14.2.3 on page 155.
4.2.1 PUSH Operation (Upstream Transaction)
The push operation takes data received from incoming H-bus/L-bus streams and passes it to an external data
buffer. This is denoted as an upstream transaction. The three required T8110 initiated burst cycles are shown
below. For more details, see Section 14.2.3 on page 155.
n
Memory read burst (fetch the write pointer information from the descriptor table).
n
Memory write burst (upload the received H-bus/L-bus data to external data buffer).
n
Memory write burst (update the write pointer information in the descriptor table).
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