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參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁(yè)數(shù)： | 99/222頁(yè) |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
97
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
8 Frame Group and FG I/O
(continued)
8.4.2 FGIO General-Purpose Bits
Any of the T8110 FG signals may be used as general-purpose I/O bits. Each FG bit used as FGIO is configured by
enabling the FGIO function via the FGx rate register(s) and setting the direction via the appropriate bits in the
FGIO R/W register. For write access to the FGIO, the FGIO data register is used to hold data for output to the FG
pin(s). Read accesses are maskable via the FGIO read mask register. For read access from the FGIO, the logical
state of the FG[7:0] signals is returned if unmasked. If an FGIO bit is masked, a read access returns 0.
8.4.3 Programmable Timer (FG7 Only)
The FG7 signal can be used as a programmable timer output, via the FG7 mode upper/lower, and FG7 counter
high and low byte registers. The FG7 timer is simply a clock divider. The FG7 counter high/low provides a 16-bit
[divider value – 1].
Note:
[divider value – 1], i.e., a value of 0000000000000011 yields a div-by-4 operation.
The FG7 mode lower register enables the counter and selects between two clock sources into the counter: either
the T8110 internal frame (8 kHz) or an external clock via the FG6 input. The FG7 mode upper register controls the
output pulse shape. The output can be inverted or noninverted and shaped as either a square wave, a carryout
pulse, or a programmable-width pulse.
n
Square wave. This option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by-
4, div-by-8, div-by-16, div-by-65536). Nonbinary divide operations while square wave is selected result in a car-
ryout pulse.
n
Carryout pulse. The output is a pulse, width = one FG7 timer clock period.
n
Programmable-width pulse. The timer output is synchronized to the T8110 32.768 MHz clock domain and can be
programmed for 1, 2, 3, or 4, 32.768 MHz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns).
8.4.4 FG External Interrupts
All FG signals are internally connected as inputs to the interrupt controller logic. Any FG signal, whether an output
or an input, may be used to trigger interrupts. When a T8110 FG signal is used as an externally sourced input into
the interrupt controller logic, it must be in input mode (i.e., shut-off, FGx rate register(s) FxRSR = 0000 0000). An
FG signal in output mode may also be used for interrupts (i.e., an 8 kHz periodic signal, see Section 8.4.1 on page
96). The interrupt control registers (0x00600—603) control how the FG inputs are handled (for more details, refer
to Section 12.1 on page 113).
8.4.5 FG Diagnostic Test Point Observation
Any of the T8110 FG signals may be used to observe a predefined set of internal test-points. Each FG bit used as
a test-point output is enabled via diagnostic register 0x00140, FG test-point enable. Settings in this register over-
ride the FGx rate and FGIO R/W register, and force the selected bits to be test-point outputs, see Section 13.1 on
page 128 and Table 103 on page 128.
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