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參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁(yè)數(shù)： | 137/222頁(yè) |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
135
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
13 Test and Diagnostics
(continued)
13.2 Diagnostic Circuit Operation
The T8110 internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions
include the following:
n
DIAG0—3, observability of internal test-points via FG(7:0), GP(7:0):
— Internal test-points are brought to chip I/O at FG and GP signals. Refer to Table 104 on page 129 and
Table 106 on page 131 for test-point assignment.
n
DIAG4—5, internal state counter diagnostic modes:
— Break counter carry chains—this is used in conjunction with monitoring of the state counter bits at FG and GP,
and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]).
— Shorten frame operation—the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input.
The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz.
This is used in conjunction with the state counter modulo function, which when properly programmed allows
the internal state counter to roll over coincident with the /FR_COMP frame center.
n
DIAG6, microprocessor access to the virtual channel memory and minibridge register regions:
— The VC memory region is only functionally applicable for packet payload switching, which is only available
when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected,
this diagnostic setting allows direct access to the virtual channel memory.
— The minibridge registers are only functionally applicable for minibridge port operation and are only available
when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected,
this diagnostic setting allows direct access to the minibridge registers.
n
DIAG6, forced RESET of analog APLL1 feedback dividers:
— The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be
held in a reset state.
n
DIAG7, external buffer RETRY timer:
— The external buffer access protocol allows for one RETRY of a descriptor table fetch in the case of a locked
external buffer. This diagnostic register allows for manipulation of the amount of time to wait before retrying a
descriptor table fetch. Please see Section 14.2.3.4 on page 160 for more details.
n
DIAG8, interrupt controller diagnostics:
— When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0]
inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the
FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits
from each tier group. Please see Section 12.2 on page 125 for more details.
n
DIAG9, interrupt controller deassertion delay:
— Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts.
n
DIAG10—11, sync-to-frame command delay:
— Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock com-
mands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| T811004 | 制造商:E-SWITCH 制造商全稱(chēng):E-SWITCH 功能描述:E-SWITCH 800SP9B5M2QE |
| T-8110---BAL-DB | 制造商:LSI Corporation 功能描述:Switch Fabric 4K x 4K 3.3V 272-Pin BGA |
| T8110L | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T-8110L | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T81110 | 制造商:Allied Controls Incorporated 功能描述:Conn Relay Socket SKT 8 POS Solder Lug ST Panel Mount |
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