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參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 173/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
171
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
15 Electrical Characteristics
(continued)
Table 128. L_SC[3:0] and Frame Group Rise and Fall Time
* Worst-case loading of 50 pF on all outputs.
Parameter
Min
—
—
—
—
Typ
—
—
—
—
Max
5
4
3
3
Unit*
ns
ns
ns
ns
L_SCx Rise Time
L_SCx Fall Time
Frame Group Rise Time
Frame Group Fall Time
15.7 Hot-Swap
The T8110 has features which assist in H.110 hot swap
applications. All H.110 bus signals are put in high imped-
ance (3-state and/or input) during the early power phase
of board insertion/removal. The ECTF H.110 specifica-
tion requires that all CT data lines and CT_NETREF
clocks have 0.7 V applied through 18 k
resistors before
plugging into and releasing from the H.110 bus. A fea-
ture on the T8110 incorporates all 34 18 k
precharge
resistors internally (32 for the CT data signals, 2 for
NETREFs). These resistors accept 0.7 V directly
through the VPRECHARGE input. The ECTF H.110
specification requires that the T8110 must be powered
from early power in hot swap applications. The circuit
that generates the 0.7 V precharge voltage must also be
powered from early power. Refer to ECTF H.110 and
PICMG CompactPCI Hot Swapspecifications for hot
swap requirements.
15.7.1 LPUE (Local Pull-Up Enable)
LPUE is used as an assist in CompactPCIspecifically
for Hot Swap; see Section 2.3.2 on page 18. During live
board insertion/removal, the only devices which should
be on early power are the power controller and interface
parts (PCI interface attached to J1, H.110 interface
attached to J4). Without the LPUE, any device con-
nected to the T8110 would get current flow from the
early power through the pull-up resistors. When late
power parts power up, they already have current flowing
through the I/O and these devices could possibly latch
up. The current flow is eliminated by LPUE disabling the
pull-up resistors. LPUE is typically controlled by the
power controller. The power controller will pull LPUE low
during board insertion/removal and will release LPUE
high so that the pull ups are re-enabled with late power
turning on. Signals that have pull-ups disabled by LPUE
are GP[7:0], FG[7:0], MB_D[15:0], LD[31:0], LREF[7:0],
PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.
15.8 Decoupling
Decoupling the T8110 V
DD
s
with 0.1
μ
F capacitors is
recommended. 1000 pF or 0.01
μ
F capacitors may be
used in addition to the 0.1
μ
F capacitors to provide addi-
tional decoupling.
15.9 APLL V
DD
Filter
Separate V
DD
s
are provided for APLL1 and APLL2 for
filtering purposes. V
DD
filtering will provide stability in the
APLL, primarily the VCOs. An R/C low pass filter should
be applied to the PLL V
DD
s
, see Figure 62. Depending
on the quality of V
DD
and board layout characteristics,
the R/C values should be selected to filter out unwanted
frequencies above a targeted frequency. For example, a
25
resistor and 10
μ
F capacitor will have a cut-off
frequency of 636 Hz. Characterize the quality of your
V
DD
and select component values accordingly. 25
is
the maximum recommended resistor value. At high fre-
quencies the ESR of a bulk cap becomes a problem (no
longer effectively low passes) so a high-frequency cap of
0.1
μ
F or so is required to compensate for some of the
higher clocks and various harmonics. This needs to be
placed as close to the T8110 device as possible to mini-
mize the radiational pick-up in the remaining trace
length. APLL1 and APLL2 each draw approximately
7 mA at 3.3 V. Hot swap applications can use late power
to ensure the capacitance and in-rush current do not vio-
late the PICMG Hot Swap specification.
0995(F)
Figure 62. APLL V
DD
Filtering
V
SS
T8110
APLL1V
DD
V
SS
APLL2V
DD
V
DD
= 3.3 V
V
DD
= 3.3 V
R
C
R
C
0.1
μ
F
0.1
μ
F
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