- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T8110 Version History PDF資料下載
參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 128/222頁 |
| 文件大小： | 2343K |
| 代理商： | T8110 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁當前第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
126
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
12 Error Reporting and Interrupt Control
(continued)
12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0]
Up to 16 of the 48 interrupt inputs are sourced external to the T8110, via the FG[7:0] and GP[7:0] signals. Each
input is independently controlled via the interrupt control registers (refer to Section 12.1.1 on page 113 and Section
12.1.2 on page 115). Any externally sourced interrupt may be presented as active-high level, active-low level, pos-
itive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked
is held in an interrupt pending register, and presented to the arbitration circuit for servicing.
12.2.2 Internally Sourced System Error Interrupts
Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126—127;
refer to Section 6.2.5 on page 59). Each of these inputs is independently controlled via the interrupt control regis-
ters (refer to Section 12.1.3 on page 116). All internal system error bit interrupts are presented as active-high level
sense. Each system error bit interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt
pending register and presented to the arbitration circuit for servicing.
12.2.3 Internally Sourced Clock Error Interrupts
Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits
(0x00122—123; refer to Section 6.2.1 on page 56). Each of these inputs is independently controlled via the inter-
rupt control registers (refer to Section 12.1.6 on page 119). All internal clock error bit interrupts are presented as
active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held
in an interrupt pending register and presented to the arbitration circuit for servicing.
12.2.4 Arbitration of Pending Interrupts
The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitra-
tion, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported
to the system via the SYSERR signal (and the PCI_INTA# signal, if enabled to do so).
12.2.4.1 Arbitration Off
This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes
place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of
the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode.
12.2.4.2 Flat Arbitration
The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt
wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered,
and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to
the current in-service interrupt (refer to Section 12.2.8 on page 127), after which the next arbitration cycle takes
place.
12.2.4.3 Tier Arbitration
The tier arbitration creates three prioritized groups as shown below:
n
Highest priority. The 16 internal latched clock error register bits.
n
Next highest priority. The 16 internal system error register bits.
n
Lowest priority. The 16 external FG[7:0] and GP[7:0] bits.
相關PDF資料 |
PDF描述 |
|---|---|
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8502 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8503 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8531A | T8531A/8532 Multichannel Programmable Codec Chip Set |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T811004 | 制造商:E-SWITCH 制造商全稱:E-SWITCH 功能描述:E-SWITCH 800SP9B5M2QE |
| T-8110---BAL-DB | 制造商:LSI Corporation 功能描述:Switch Fabric 4K x 4K 3.3V 272-Pin BGA |
| T8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T-8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T81110 | 制造商:Allied Controls Incorporated 功能描述:Conn Relay Socket SKT 8 POS Solder Lug ST Panel Mount |
發(fā)布緊急采購，3分鐘左右您將得到回復。