
218
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
R3SLR
R3WLR
R3HLR
A3SLR
W3SLR
W3WLR
W3HLR
A3HLR
R4SLR
R4WLR
R4HLR
A4SLR
W4SLR
W4WLR
W4HLR
A4HLR
R5SLR
R5WLR
R5HLR
A5SLR
W5SLR
W5WLR
W5HLR
A5HLR
R6SLR
R6WLR
R6HLR
A6SLR
W6SLR
W6WLR
W6HLR
A6HLR
R7SLR
R7WLR
R7HLR
A7SLR
W7SLR
W7WLR
W7HLR
A7HLR
IC0SB
MB_CS3 read cycle setup
MB_CS3 read cycle width
MB_CS3 read cycle hold
MB_CS3 address setup
MB_CS3 write cycle setup
MB_CS3 write cycle width
MB_CS3 write cycle hold
MB_CS3 address hold
MB_CS4 read cycle setup
MB_CS4 read cycle width
MB_CS4 read cycle hold
MB_CS4 address setup
MB_CS4 write cycle setup
MB_CS4 write cycle width
MB_CS4 write cycle hold
MB_CS4 address hold
MB_CS5 read cycle setup
MB_CS5 read cycle width
MB_CS5 read cycle hold
MB_CS5 address setup
MB_CS5 write cycle setup
MB_CS5 write cycle width
MB_CS5 write cycle hold
MB_CS5 address hold
MB_CS6 read cycle setup
MB_CS6 read cycle width
MB_CS6 read cycle hold
MB_CS6 address setup
MB_CS6 write cycle setup
MB_CS6 write cycle width
MB_CS6 write cycle hold
MB_CS6 address hold
MB_CS7 read cycle setup
MB_CS7 read cycle width
MB_CS7 read cycle hold
MB_CS7 address setup
MB_CS7 write cycle setup
MB_CS7 write cycle width
MB_CS7 write cycle hold
MB_CS7 address hold
Invert MB CS0 strobe
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Select
0x00730
0x00731
0x00732
0x00733
0x00734
0x00735
0x00736
0x00737
0x00740
0x00741
0x00742
0x00743
0x00744
0x00745
0x00746
0x00747
0x00750
0x00751
0x00752
0x00753
0x00754
0x00755
0x00756
0x00757
0x00760
0x00761
0x00762
0x00763
0x00764
0x00765
0x00766
0x00767
0x00770
0x00771
0x00772
0x00773
0x00774
0x00775
0x00776
0x00777
0x00780
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
Table 134. Mnemonic Summary, Sorted by Register
(continued)
Mnemonic
Description
Type
Register
Bit Position