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參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 32/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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30
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
(continued)
4.1.4.2 Delayed Read Transaction
Only one delayed read from the data memory may be queued at a time. A delayed read transaction latches the
address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries
the same transaction
or
attempts a different read transaction from data memory prior to the queued delayed read
completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same trans-
action after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; please refer to
Figure 8). Any subsequent posted write attempts to the data memory while a delayed read is in progress result in
an error condition, and the delayed read and the posted write attempts are ignored. Error is reported at register sta-
tus 7, bit 0 (refer to Section 6.2.5 on page 59).
4.1.5 Virtual Channel Memory Space Target Access
The T8110 virtual channel memory is not guaranteed to be immediately available for access. Access to this mem-
ory is prioritized for H-bus/L-bus switching and packet payload switching with PCI target access allowed as the
lowest priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the
virtual channel memory. Upon reception of a PCI read or write request, if the virtual channel memory is immediately
available, the transaction is completed as normal single-cycle access (refer to Figure 6 and Figure 8). If the virtual
channel memory is not available at the time of the request, any write cycle is posted and any read cycle becomes
a delayed read (for more detail on virtual channel memory programming; refer to Section 14.1.1.2 on page 138). A
detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity
errors on write transactions are still posted to the PCI core interface, but are discarded.
4.1.5.1 Posted Write Transaction
Only one posted write to the virtual channel memory may be queued at a time. Refer to Figure 6. The user
must
monitor a status bit (register status 8, bit 1; refer to Section 6.2.7) to determine whether a posted write is already
queued before attempting more writes. Subsequent posted write attempts to the virtual channel memory while a
queued posted write has not completed result in an error condition, and both writes (the queued one and the sub-
sequent one) are ignored. Error is reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59). Subse-
quent read attempts from the virtual channel memory while a posted WRITE is queued result in a target retry (refer
to Figure 10).
4.1.5.2 Delayed Read Transaction
Only one delayed read from the virtual channel memory may be queued at a time. A delayed read transaction
latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the ini-
tiator retries the same transaction
or
attempts a different read transaction from virtual channel memory prior to the
queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator
retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle
read; refer to Figure 8). Any subsequent posted write attempts to the virtual channel memory while a delayed read
is in progress result in an error condition, and the delayed read and the posted write attempts are ignored. Error is
reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59).
4.1.6 Minibridge Space Target Access
The T8110 minibridge port is not guaranteed to be immediately available for access. Access time to this space is
dependent on wait-state control register setups. Because there is a potential variable amount of latency, target
burst transfers are not allowed to the minibridge port. All write cycles are posted writes. All read cycles are delayed
reads. Refer to the Minibridge section, starting on page 107, for more details on minibridge control and operation.
A detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity
errors on write transactions are still posted to the PCI core interface, but are discarded.
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