80
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
7 Clock Architecture
(continued)
7.4.5.1 Phase Alignment
Phase alignment allows the free-running internally generated clocks to be forced into alignment with the incoming
main selection clock and frame, under the following conditions:
n
The main selection clock is based on a paired bit clock/frame reference (see Section 7.4.1.2 on page 78),
and
the phase alignment circuit is enabled (via register 0x00107, phase alignment select).
The incoming frame center is monitored via the frame center samplers (see Section 7.4.1.2 on page 78) and com-
pared to the state of the internally generated frame. The circuit determines whether the frame centers are aligned.
If not, three possible actions take place as shown below:
n
NOP: no corrections when phase alignment is disabled.
n
Snap correction: the internally generated clocks and frame immediately snap into alignment with the incoming
frame center.
n
Slide correction: the internally generated clocks and frame gradually slide into alignment with the incoming frame
center, at a rate of one 65.536 MHz clock period per frame. The sliding occurs in one direction only and creates
frame periods that are 15.25 ns longer than 125
μ
s until the frames are aligned. Please refer to Figure 21.
5-9414 (F)
A. Phase Alignment—SNAP
5-9415 (F)
B. Phase Alignment—SLIDE
Figure 21. T8110 Phase Alignment, SNAP and SLIDE
INCOMING FRAME CENTER
INCOMING FRAME CENTER
MISALIGNED
INTERNAL
FRAME CENTER
SNAP
ALIGNMENT
REALIGNED INTERNAL
FRAME CENTER
125
μ
s
INCOMING BIT CLOCK
CT_C8_A
INCOMING FRAME
/CT_FRAME_A
INTERNAL CLOCK,
8.192 MHz
INTERNAL FRAME
REALIGNED INTERNAL
FRAME CENTER
MISALIGNED
INTERNAL
FRAME CENTER
MISALIGNED
INTERNAL
FRAME CENTER
MISALIGNED
INTERNAL
FRAME CENTER
INCOMING BIT CLOCK
CT_C8_A
INCOMING FRAME
/CT_FRAME_A
INTERNAL CLOCK,
8.192 MHz
INTERNAL FRAME
125
μ
s
125
μ
s
125
μ
s
45 ns
30 ns
15 ns
SLIDE ALIGNMENT
SLIDE ALIGNMENT
SLIDE ALIGNMENT