
Agere Systems Inc.
91
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
8 Frame Group and FG I/O
(continued)
8.1.2 FGx Width Registers
The FGx width registers control the polarity and the pulse widths generated for the corresponding frame group bit.
The pulse-width programming works in conjunction with the FGx rate registers to provide 1-bit, 2-bit, 4-bit,
1-byte, and 2-byte wide pulses for any of the available frame group rates (see Table 69).
8.1.3 FGx Rate Registers
The FGx rate registers either enable FGIO operation* or work in conjunction with FGx width registers to provide
various width frame group pulses at rates of 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
*
FGIO operation is controlled at registers 0x00480—482. Refer to Section 8.3 on page 93.
Table 69. FGx Width Registers
Byte
Address
Name
Bit(s) Mnemonic
Value
Function
0x00402
(0x00412)
(0x00422)
(0x00432)
(0x00442)
(0x00452)
(0x00462)
(0x00472)
FG0 Width
(FG1 Width)
(FG2 Width)
(FG3 Width)
(FG4 Width)
(FG5 Width)
(FG6 Width)
(FG7 Width)
7
F0ISB
(F1ISB)
(F2ISB)
(F3ISB)
(F4ISB)
(F5ISB)
(F6ISB)
(F7ISB)
F0WSP
(F1WSP)
(F2WSP)
(F3WSP)
(F4WSP)
(F5WSP)
(F6WSP)
(F7WSP)
0
1
Generate active-high pulse (default).
Generate active-low pulse.
6:0
000 0000
000 0001
000 0010
000 0100
001 0000
010 0000
1-bit wide pulse (default).
1-bit wide pulse.
2-bit wide pulse.
4-bit wide pulse.
1-byte wide pulse.
2-byte wide pulse.
Table 70. FGx Rate Registers
Byte Address
Name
Bit(s) Mnemonic
Value
Function
0x00403
(0x00413)
(0x00423)
(0x00433)
(0x00443)
(0x00453)
(0x00463)
(0x00473)
FG0 Rate
(FG1 Rate)
(FG2 Rate)
(FG3 Rate)
(FG4 Rate)
(FG5 Rate)
(FG6 Rate)
(FG7 Rate)
7:0
F0RSR
(F1RSR)
(F2RSR)
(F3RSR)
(F4RSR)
(F5RSR)
(F6RSR)
(F7RSR)
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0000 1001
Off (default).
FGIO enabled* (not used as a frame group).
FGx rate = 2.048 MHz.
FGx rate = 4.096 MHz.
FGx rate = 8.192 MHz.
FGx rate = 16.384 MHz.