36
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
(continued)
Notes:
T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of
PCI_DEVSEL#.
A configuration read access cycle takes six PCI clocks.
Figure 15. T8110 PCI Interface
—
Configuration READ Cycle
4.3.1 Loadable PCI Configuration Space Via EEPROM
The T8110 allows a user-definable subsystem ID and subsystem vendor ID field (configuration space address
0x2C). Immediately after power-on reset or PCIRST#, the T8110's PCI core loads the read-only configuration reg-
isters sequentially from the first 64 bytes in the EEPROM. All values are ignored, except for the subsystem ID, sub-
system vendor ID, MAX_LAT, MIN_GNT, and INTERRUPT_PIN (bytes 44—63). Ignored values (bytes 0—43) are
don't care and exist simply as placeholders. During the EEPROM operation,
all
PCI target accesses to the T8110
result in a target retry.
Note:
If no EEPROM is present, internal pull-down resistors will set the values for subsystem ID, subsystem ven-
dor ID, MAX_LAT, MIN_GNT, and INTERRUPT_PIN to zero. After the PCI core loads the values into config-
uration registers, this space is read-only. The only way to change the values from 0 is from an external
EEPROM.
Four pins are required for the EEPROM interface. The following pins are used for EEPROM just at power-on:
MB_A[1] = EE_DO_IN (input, data output from EEPROM)
MB_A[2] = EE_DI_OUT (output, data input to EEPROM)
MB_A[3] = EE_SK_OUT (output, clock input to EEPROM)
EE_CS_OUT = EE_CS_OUT (output, chip select input to EEPROM)
The interface protocol follows the standard 93C46 EEPROM (refer to Figure 16). A state machine within the
T8110's PCI core produces nine read cycles, one for each of the read-only configuration register fields. Only the
subsystem ID, subsystem vendor ID, MAX_LAT, MIN_GNT, and interrupt pin fields are configurable. All other fields
returned by the EEPROM are ignored, but must be present as placeholders.
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_IDSEL
PCI_DEVSEL#
PCI_CLK
PCI_AD[31:0]
PCI_CBE#[3:0]
PCI_STOP#
PCI_PAR
ADDR
DATA
CFG RD
(0xA)
Byte Enable
Addr
Parity
XXXXX
Data
Parity
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXX