24
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
(continued)
0x00400
0x00410
0x00420
0x00430
0x00440
0x00450
0x00460
0x00470
0x00474
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.2
FG0 rate
FG1 rate
FG2 rate
FG3 rate
FG4 rate
FG5 rate
FG6 rate
FG7 rate
FG7 mode upper
FG0 width
FG1 width
FG2 width
FG3 width
FG4 width
FG5 width
FG6 width
FG7 width
FG7 mode lower
FG0 upper start
FG1 upper start
FG2 upper start
FG3 upper start
FG4 upper start
FG5 upper start
FG6 upper start
FG7 upper start
FG7 counter high
byte
FGIO read mask
GPIO read mask
FGIO interrupt
enable
GPIO interrupt
enable
System interrupt
pending, upper
Clock interrupt
pending, upper
PCI_INTA output
select
Reserved
FG0 lower start
FG1 lower start
FG2 lower start
FG3 lower start
FG4 lower start
FG5 lower start
FG6 lower start
FG7 lower start
FG7 counter low byte
0x00480
0x00500
0x00600
8.3
9.1
12.1
Reserved
GPIO override
FGIO interrupt polarity
FGIO R/W
GPIO R/W
Reserved
FGIO data register
GPIO data register
FGIO interrupt
pending
GPIO interrupt
pending
System interrupt
pending, lower
Clock interrupt
pending, lower
Arbitration control
0x00604
12.1
GPIO interrupt polarity
Reserved
0x00608
12.1
System interrupt enable,
upper
Clock interrupt enable,
upper
CLKERR output select
System interrupt
enable, lower
Clock interrupt
enable, lower
SYSERR output
select
SYSERR pulse
width
In-service, byte 2
0x0060C
12.1
0x00610
12.1
0x00614
12.1
CLKERR pulse width
Reserved
0x006FC
0x00700
0x00704
0x00710
0x00714
0x00720
0x00724
0x00730
0x00734
0x00740
0x00744
0x00750
12.1
11.1
11.1
11.1
11.1
11.1
11.1
11.1
11.1
11.1
11.1
11.1
In-service, byte 3
CS0 address setup wait CS0 read hold wait CS0 read width wait CS0 read setup wait
CS0 address hold wait
CS0 write hold wait CS0 write width wait CS0 write setup wait
CS1 address setup wait CS1 read hold wait CS1 read width wait CS1 read setup wait
CS1 address hold wait
CS1 write hold wait CS1 write width wait CS1 write setup wait
CS2 address setup wait CS2 read hold wait CS2 read width wait CS2 read setup wait
CS2 address hold wait
CS2 write hold wait CS2 write width wait CS2 write setup wait
CS3 address setup wait CS3 read hold wait CS3 read width wait CS3 read setup wait
CS3 address hold wait
CS3 write hold wait CS3 write width wait CS3 write setup wait
CS4 address setup wait CS4 read hold wait CS4 read width wait CS4 read setup wait
CS4 address hold wait
CS4 write hold wait CS4 write width wait CS4 write setup wait
CS5 address setup wait CS5 read hold wait CS5 read width wait CS5 read setup wait
In-service, byte 1
In-service, byte 0
Table 11. PCI Interface Registers Map
(continued)
DWORD
Address
(20 bits)
Section
Cross
Reference
Registers
Byte 3
Byte 2
Byte 1
Byte 0