- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T8110 Version History PDF資料下載
參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 7/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
Table of Contents
(continued)
Contents
Page
Agere Systems Inc.
5
May 2001
and Packet Payload Engine
Data Sheet
Ambassador T8110 PCI-Based H.100/H.110 Switch
12 Error Reporting and Interrupt Control ..............................................................................................................113
12.1 Interrupt Control Registers ....................................................................................................................113
12.1.1 Interrupts Via External FG[7:0] Registers ......................................................................................113
12.1.1.1 FGIO Interrupt Pending Register .......................................................................................113
12.1.2 Interrupts Via External GP[7:0] ......................................................................................................115
12.1.2.1 GPIO Interrupt Pending Register .......................................................................................115
12.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ................................................................116
12.1.3 Interrupts Via Internal System Errors .............................................................................................116
12.1.4 System Interrupt Pending High/Low Registers ..............................................................................117
12.1.5 System Interrupt Enable High/Low Registers ................................................................................118
12.1.6 Interrupts Via Internal Clock Errors ................................................................................................119
12.1.7 Clock Interrupt Pending High/Low Registers .................................................................................120
12.1.8 Clock Interrupt Enable High/Low Registers ...................................................................................121
12.1.9 Interrupt Servicing Registers ..........................................................................................................122
12.1.9.1 Arbitration Control Register ...............................................................................................122
12.1.10 PCI_INTA Output Select Register ..................................................................................................122
12.1.10.1 SYSERR and CLKERR Output Select Register ................................................................122
12.1.10.2 Interrupt In-Service Registers ...........................................................................................123
12.2 Error Reporting and Interrupt Controller Circuit Operation ....................................................................125
12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] .......................................................................126
12.2.2 Internally Sourced System Error Interrupts ....................................................................................126
12.2.3 Internally Sourced Clock Error Interrupts .......................................................................................126
12.2.4 Arbitration of Pending Interrupts ....................................................................................................126
12.2.4.1 Arbitration Off ....................................................................................................................126
12.2.4.2 Flat Arbitration ...................................................................................................................126
12.2.4.3 Tier Arbitration ...................................................................................................................126
12.2.4.3.1 Pre-Empting Disabled ..................................................................................127
12.2.4.3.2 Pre-Empting Enabled ..................................................................................127
12.2.5 CLKERR Output .............................................................................................................................127
12.2.6 SYSERR Output ............................................................................................................................127
12.2.7 PCI_INTA# Output .........................................................................................................................127
12.2.8 System Handling of Interrupts ........................................................................................................127
13 Test and Diagnostics .......................................................................................................................................128
13.1 Diagnostics Control Registers ...............................................................................................................128
13.1.1 FG Testpoint Enable Register ........................................................................................................128
13.1.2 GP Testpoint Enable Register .......................................................................................................129
13.1.3 State Counter Modes Registers .....................................................................................................132
13.1.4 Miscellaneous Diagnostics Low Register .......................................................................................133
13.1.5 External Buffer Retry Timer Register .............................................................................................134
13.2 Diagnostic Circuit Operation ..................................................................................................................135
14
Connection Control—Standard and Virtual Channel ......................................................................................136
14.1 Programming Interface ..........................................................................................................................136
14.1.1 PCI Interface ..................................................................................................................................136
14.1.1.1 PCI Connection Memory Programming .............................................................................136
14.1.1.2 PCI Virtual Channel Memory Programming ......................................................................138
14.1.2 Microprocessor Interface ...............................................................................................................139
14.1.2.1 Microprocessor Connection Memory Programming ..........................................................139
14.1.2.2 Microprocessor Virtual Channel Memory Programming ...............................................144
14.2 Switching Operation ..............................................................................................................................146
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8502 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8503 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8531A | T8531A/8532 Multichannel Programmable Codec Chip Set |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T811004 | 制造商:E-SWITCH 制造商全稱:E-SWITCH 功能描述:E-SWITCH 800SP9B5M2QE |
| T-8110---BAL-DB | 制造商:LSI Corporation 功能描述:Switch Fabric 4K x 4K 3.3V 272-Pin BGA |
| T8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T-8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T81110 | 制造商:Allied Controls Incorporated 功能描述:Conn Relay Socket SKT 8 POS Solder Lug ST Panel Mount |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。