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參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 129/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
127
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
12 Error Reporting and Interrupt Control
(continued)
Arbitration assigns interrupt servicing priority to the three groups. Multiple pending interrupts within the same group
are arbitrated round-robin. When a pending interrupt wins the arbitration, the in-service register is loaded with its
corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next
arbitration cycle.
12.2.4.3.1 Pre-Empting Disabled
With pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with
its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to
respond to the current in-service interrupt (refer to Section 12.2.8 on page 127), at which time another arbitration
cycle takes place.
12.2.4.3.2 Pre-Empting Enabled
With pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register
and SYSERR has been triggered) can be overridden by new incoming pending interrupts of higher priority. The
current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the
in-service register and SYSERR is retriggered. Once all interrupts of higher priority have been serviced by the sys-
tem (refer to Section 12.2.8 on page 127), the stack is popped and the original lower-priority interrupt is reissued.
12.2.5 CLKERR Output
The CLKERR output signal is used to indicate any internal clocking errors. The trigger for the CLKERR output is
simply a logical OR of the internal latched clock error register bits. All bits of the internal clock error register must
be cleared in order to rearm the CLKERR trigger. The CLKERR trigger induces a state machine to generate the
CLKERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-
low single pulse.
12.2.6 SYSERR Output
The T8110 SYSERR output signal is used to report interrupts. Internally, the arbitration circuit provides a SYSERR
trigger, which induces a state machine to generate the SYSERR signal in one of four possible ways: active-high
level, active-low level, active-high single pulse, or active-low single pulse.
12.2.7 PCI_INTA# Output
The internal SYSERR trigger can be enabled to also trigger a PCI interrupt via the PCI_INTA# signal.
12.2.8 System Handling of Interrupts
The T8110 interrupt controller presents an interrupt to the system by triggering the SYSERR output and providing
a predefined interrupt vector value at the interrupt in-service register (ISR). The system may acknowledge the
interrupt in three ways as shown below:
n
System reads the T8110 ISR register. This allows the arbiter to advance, and if more pending interrupts are
active, reloads the ISR with the winner of the arbitration and retriggers SYSERR.
n
System clears the T8110 ISR register (via register 0x00100, soft reset; write 0x20 clears the ISR). The arbiter
advances, and if more pending interrupts are active, reloads the ISR and retriggers SYSERR.
n
System resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the ISR and all the
pending interrupt registers). All pending interrupts are cleared, and the arbiter is reset.
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