Agere Systems Inc.
13
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
2 Pin Description
(continued)
Table 9. T8110 Pinouts
(continued)
Minibridge Interface
(continued)
Ball
H2
H3
J4
J1
J2
W1
V1
V2
U3
U1
U2
T3
T4
T1
T2
R3
P4
R1
R2
P2
P3
N1
P1
L1
L2
M1
M2
M3
M4
N2
N3
Pin Name
MB_A5/UP_A5
MB_A6/UP_A6
MB_A7/UP_A7
MB_A8/UP_A8
MB_A9/UP_A9
MB_D0
MB_D1
MB_D2
MB_D3
MB_D4
MB_D5
MB_D6
MB_D7
MB_D8
MB_D9
MB_D10
MB_D11
MB_D12
MB_D13
MB_D14
MB_D15
MB_RD/UP_RD#(DS#)
MB_WR/UP_WR#(R/W#)
MB_CS0/UP_A16
MB_CS1/UP_A17
MB_CS2/UP_A18
MB_CS3/UP_A19
MB_CS4/UP_CSN
MB_CS5/UP_WB_SEL
MB_CS6/UP_RDY(DTACK#)
MB_CS7/IM_SEL
Buffer Type
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA 3-state
8 mA I/O-Schmitt
H-Bus Interface
Op amp noninvert
Input
Input
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
Pull-Up/Down
(see note on page 11)
20 k
down
20 k
down
20 k
down
20 k
down
20 k
down
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
LPUE: 50 k
up
20 k
down
20 k
down
20 k
down
20 k
down
LPUE: 50 k
up
LPUE: 50 k
up
External pull-up required
LPUE: 50 k
up
C1
D5
D7
A11
B11
C10
C11
A10
B10
VPRECHARGE
H110_ENABLE
H100_ENABLE
CT_D0
CT_D1
CT_D2
CT_D3
CT_D4
CT_D5
—
20 k
down
20 k
down
Enabled: 50 k
up/20 k
Vpre
Enabled: 50 k
up/20 k
Vpre
Enabled: 50 k
up/20 k
Vpre
Enabled: 50 k
up/20 k
Vpre
Enabled: 50 k
up/20 k
Vpre
Enabled: 50 k
up/20 k
Vpre