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參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁(yè)數(shù)： | 24/222頁(yè) |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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22
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
The T8110 provides a selection of two interface mechanisms via the VIO/
μ
P_SELECT input. This must be a static
signal (either pulled high or pulled low).
n
VIO/
μ
P_SELECT tied to GND = T8110 interface to a microprocessor bus, connected via the minibridge port.
n
VIO/
μ
P_SELECT tied to 3.3 V = T8110 interface to a local PCI bus, 3.3 V signaling.
n
VIO/
μ
P_SELECT tied to 5 V = T8110 interface to a local PCI bus, 5 V signaling.
The T8110 is a single-function PCI device; it can act as a target or an initiator. All addressing is DWORD aligned for
32-bit data transfers. Refer to Section 2.1 on page 8 for pin descriptions. When the PCI interface is selected, the
minibridge port functions as a bridge to convert the PCI access protocol into a simple handshake protocol for exter-
nal, non-PCI devices connected to this port. For more details, see Section 11, starting on page 107.
The PCI interface is arranged to provide a mixture of accesses. Initialization and register programming is typically
under coprocessor control. As a result, the T8110 operates as a slave when being programmed by the coprocessor
or by the host via a PCI-PCI bridge. Diagnostics and error handling are also defined as slave operations. However,
when packets are processed by either taking data from the H1x0 bus and passing it to memory, or when data is
retrieved from memory and sent to the H1x0 bus, the T8110 operates as a master, arbitrating for the bus and taking
control of its own burst transactions. This ensures that the bandwidth required by the T8110 as a local PCI bus
owner is kept to a minimum. Packet transactions are not limited to the H1x0 bus and local time slots can be routed
to and from the PCI bus as well.
4.1 Target
The T8110 PCI bus interface allows target access to five internal regions: registers, connection memory, data
memory, virtual channel memory, and the minibridge. Target burst transactions are only allowed to the register and
connection memory space. No target bursts are allowed to/from the data memory, virtual channel memory, or the
minibridge space. All target accesses get synchronized between the PCI’s 33 MHz clock domain and the T8110's
internal 65.536 MHz clock domain. Of the 32 bits of address provided, the upper 12 decode the base address,
while the lower 20 provide addressing for the internal regions of the T8110, as shown in Table 10.
Table 10. T8110 Memory Mapping to PCI Space
Region
Subregion
Reserved
Range (hex)
0x00000—0x000FF
0x00100—0x001FF
0x00200—0x002FF
0x00300—0x003FF
0x00400—0x004FF
0x00500—0x005FF
0x00600—0x006FF
0x00700—0x007FF
0x00800—0x0FFFF
0x10000—0x1FFFF
0x20000—0x2FFFF
0x30000—0x3FFFF
0x40000—0x4FFFF
0x50000—0x6FFFF
0x70000—0x7FFFF
0x80000—0xFFFFF
Registers
Operating control and status
Clocks
Rate control
Frame group
General-purpose I/O
Interrupt control
Minibridge control
Reserved
—
—
—
—
—
—
—
Virtual channel memory
Data memory
Reserved
Connection memory
Reserved
Minibridge
Reserved
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