- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T8110 Version History PDF資料下載
參數(shù)資料
| 型號： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 151/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁當(dāng)前第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
Agere Systems Inc.
149
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
14
Connection Control—Standard and Virtual Channel
(continued)
14.2.1.3 Virtual Channel Memory
The T8110 virtual channel memory consists of 512 locations, one location for each possible virtual channel. Virtual
channel memory consists of two portions, static and scratchpad, and controls how the VC portion of the data mem-
ory is partitioned when the data memory is configured to allow for virtual channels (refer to Figure 49). The data
memory partition for a virtual channel is defined by the static portion of the virtual channel memory (refer to
Figure 39 and Figure 40), which includes the following information:
n
SBA (static base address) is the physical start address for this particular virtual channel in the data memory VC
space.
n
STD (static depth) is the total number of bytes (in DWORDS) allotted for this virtual channel. A virtual channel
can occupy 2 DWORDS (minimum) up to 64 DWORDS (maximum) in the data memory VC space.
The scratchpad portion of the virtual channel memory (refer to Figure 39 and Figure 41) keeps track of the current
data memory address within the data memory partition as follows:
n
SPCD (scratchpad current depth) is the current number of bytes transferred to/from serial streams.
n
SPCO (scratchpad current offset) is the data memory address pointer.
14.2.2 Standard Switching
Standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex
connections (refer to Figure 36 on page 137, Figure 43 on page 141, and Section 14.2.1.1 on page 146).
14.2.2.1 Constant Delay and Minimum Delay Connections
The VFC control bit in connection memory determines which of two data pages is accessed, when the data mem-
ory is configured to double-buffering for telephony connections (refer to Figure 49). This bit always affects
to
con-
nections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. This bit can
control a
from
connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the VFC bit
has no bearing on
from
connections.
The double-buffering configuration creates two data pages. During a particular frame (125
μ
s time boundary, parti-
tioned into time-slots), one page is the active page, the other is the inactive page. The active/inactive page status
toggles at every frame boundary. For all
from
connections (except for subrate connections), incoming serial data is
always written to the active page. For all
to
connections, the VFC control bit indicates whether to read from the
active or inactive page. Manipulation of this bit affects the latency between the incoming
from
data and the outgo-
ing
to
data. This latency defines whether or not a connection is constant delay or minimum delay.
Please see Appendix A on page 190 for more details on constant and minimum delay connections.
14.2.2.2 Pattern Mode
The PME control bit in connection memory affects only
to
connections. Instead of reading a value out of the data
memory for subsequent output to a serial stream, the lower 8 bits of the TAG field provide a byte pattern for the
serial output.
14.2.2.3 Subrate
The subrate control bit field in connection memory is used only by
from
connections and controls how individual
bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to
achieve subrate switching.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8502 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8503 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8531A | T8531A/8532 Multichannel Programmable Codec Chip Set |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T811004 | 制造商:E-SWITCH 制造商全稱:E-SWITCH 功能描述:E-SWITCH 800SP9B5M2QE |
| T-8110---BAL-DB | 制造商:LSI Corporation 功能描述:Switch Fabric 4K x 4K 3.3V 272-Pin BGA |
| T8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T-8110L | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ambassador㈢ T8110L H.100/H.110 Switch |
| T81110 | 制造商:Allied Controls Incorporated 功能描述:Conn Relay Socket SKT 8 POS Solder Lug ST Panel Mount |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。