Agere Systems Inc.
217
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
JC7EB
JC8EB
JC9EB
JCAEB
JCBEB
JCCEB
JCDEB
JCEEB
JCFEB
JAMSR
JSPSR
JSOSR
JCOSR
JSWSR
JCWSR
JISOR
JVLOR
JVHOB
R0SLR
R0WLR
R0HLR
A0SLR
W0SLR
W0WLR
W0HLR
R1SLR
R1WLR
R1HLR
A1SLR
W1SLR
W1WLR
W1HLR
A1HLR
R2SLR
R2WLR
R2HLR
A2SLR
W2SLR
W2WLR
W2HLR
A2HLR
Interrupt from CLKERR 7
Interrupt from CLKERR 8
Interrupt from CLKERR 9
Interrupt from CLKERR A
Interrupt from CLKERR B
Interrupt from CLKERR C
Interrupt from CLKERR D
Interrupt from CLKERR E
Interrupt from CLKERR F
Interrupt arbitration mode
Interrupt SYSERR-to-PCI_INTA
Interrupt SYSERR output mode
Interrupt CLKERR output mode
Interrupt SYSERR pulse width
Interrupt CLKERR pulse width
Interrupt in-service
Interrupt in-service VC ID low
Interrupt in-service VC ID high
MB_CS0 read cycle setup
MB_CS0 read cycle width
MB_CS0 read cycle hold
MB_CS0 address setup
MB_CS0 write cycle setup
MB_CS0 write cycle width
MB_CS0 write cycle hold
MB_CS1 read cycle setup
MB_CS1 read cycle width
MB_CS1 read cycle hold
MB_CS1 address setup
MB_CS1 write cycle setup
MB_CS1 write cycle width
MB_CS1 write cycle hold
MB_CS1 address hold
MB_CS2 read cycle setup
MB_CS2 read cycle width
MB_CS2 read cycle hold
MB_CS2 address setup
MB_CS2 write cycle setup
MB_CS2 write cycle width
MB_CS2 write cycle hold
MB_CS2 address hold
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Select
Select
Select
Select
Select
Select
Output
Output
Output
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
0x0060E
0x0060F
0x0060F
0x0060F
0x0060F
0x0060F
0x0060F
0x0060F
0x0060F
0x00610
0x00611
0x00612
0x00613
0x00616
0x00617
0x006FC
0x006FE
0x006FF
0x00700
0x00701
0x00702
0x00703
0x00704
0x00705
0x00706
0x00710
0x00711
0x00712
0x00713
0x00714
0x00715
0x00716
0x00717
0x00720
0x00721
0x00722
0x00723
0x00724
0x00725
0x00726
0x00727
7
0
1
2
3
4
5
6
7
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 134. Mnemonic Summary, Sorted by Register
(continued)
Mnemonic
Description
Type
Register
Bit Position