128
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
13 Test and Diagnostics
13.1 Diagnostics Control Registers
The diagnostic control registers allow for various diagnostic modes (refer to Section 13.2 on page 135).
13.1.1 FG Testpoint Enable Register
The FG test-point enable register allows individual programming of FG[7:0] bits for either standard operation (as
FG or FGIO) or as test-point outputs. FG test-point select controls the MUX selection for which test-points are
selected. Refer to Table 104 on page 129 for test-point assignments for each FG bit.
Table 102. Diagnostics Control Register Map
DWORD
Address
(20 bits)
Register
Byte 3
Byte 2
Byte 1
Byte 0
0x00140 Diag3, GP test-point
select
0x00144 Diag7, external buffer
RETRY timer
0x00148 Diag11, sync-to-
frame command off-
set high
Diag2, GP test-point
enable
Diag6, miscellaneous
diagnostics low
Diag10, sync-to-
frame command off-
set low
Diag1, FG test-point select Diag0, FG test-point
enable
Diag4, state counter
modes low
Diag8, interrupt controller
diagnostics
Diag5, state counter
modes high
Diag9, interrupt controller
SYSERR delay
Table 103. FG Testpoint Enable Registers
Byte
Address
Name
Bit(s) Mnemonic
Value
Function
0x00140 Diag0, FG Testpoint
Enable
7
FT7EB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FG7 is standard FG or FGIO bit (default).
FG7 is a test-point.
FG6 is standard FG or FGIO bit (default).
FG6 is a test-point.
FG5 is standard FG or FGIO bit (default).
FG5 is a test-point.
FG4 is standard FG or FGIO bit (default).
FG4 is a test-point.
FG3 is standard FG or FGIO bit (default).
FG3 is a test-point.
FG2 is standard FG or FGIO bit (default).
FG2 is a test-point.
FG1 is standard FG or FGIO bit (default).
FG1 is a test-point.
FG0 is standard FG or FGIO bit (default).
FG0 is a test-point.
LLLL LLLL Value for MUX selection of test-points
output to FG[7:0]—see Table 103 on
page 128.
6
FT6EB
5
FT5EB
4
FT4EB
3
FT3EB
2
FT2EB
1
FT1EB
0
FT0EB
0x00141 Diag1, FG Testpoint
Select
7:0
FTPSR