162
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
14
Connection Control—Standard and Virtual Channel
(continued)
14.2.3.4.3 External Buffer
Each virtual channel has an allotment of external buffer space. The external buffer for a virtual channel can be
thought of as a FIFO, with the T8110 controlling one side, and the
USER
controlling the other. The base address
and the last address offset of the external buffer is stored in the descriptor table (first DWORD of the entry for the
corresponding virtual channel; see previous section). Each external buffer is defined as 4 Kbytes, with the base
address at 4 Kbyte boundaries. An external buffer is not limited to exactly 4 Kbytes—it can be smaller or larger,
which requires special on-the-fly manipulation of the descriptor table by the
USER
side (refer to Section
14.2.3.4.4). The only basic requirement for the external buffer size is that it be an integral multiple of the T8110
internal buffer size for a given virtual channel.
14.2.3.4.4 Transfer Protocol
The transfer mechanism between the T8110 and the
USER
is three T8110-initiated PCI transfers: descriptor table
fetch, external buffer data transfer, and descriptor table update (refer to Figure 12 and Figure 13). The second
transfer (external buffer data transfer) would normally occur; however, it may not occur if the state of the descriptor
table control and status flags shows the external buffer not accessible by the T8110.
14.2.3.4.4.1 Descriptor Table Fetch
T8110 uses the descriptor table base address stored in its control register field (address 0x00110—113), and adds
an address offset determined by which of the possible 512 virtual channels initiated the action to create the
descriptor table address for that channel. The transfer is a PCI memory read burst of 2 DWORDS. The descriptor
table contents are decoded, and a number of calculations are performed on the descriptor table data. The results
of these calculations determine the sequence of further PCI transfers (i.e., whether or not to skip the second exter-
nal buffer data transfer, and what value(s) to update the descriptor table with). Refer to Figure 58 and Table 116.
Table 116. Descriptor Table GBS Status Descriptions
GBS Value
Status Description
000
001
010
011
100
101
110
111
USER
has initialized the external buffer.
T8110 has completed with normal status.
T8110 has completed with a boundary condition.
T8110 has overwritten a portion of the external buffer unread by
USER.
USER
has initialized the T8110 pointer (TF and TOR).
T8110 did not complete due to a locked buffer.
T8110 did not complete due to stalled buffer (boundary condition).
USER
has disabled the external buffer.