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參數(shù)資料
| 型號(hào)： | T8110 |
| 英文描述： | Version History |
| 中文描述： | 版本歷史 |
| 文件頁數(shù)： | 31/222頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | T8110 |
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Agere Systems Inc.
29
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
4 PCI Interface
(continued)
4.1.2 Register Space Target Access
The T8110 registers are always immediately available for access. Read and write bursting is allowed to this region.
Read access to reserved addresses returns 0x00. For more details on register programming; refer to Section 6,
starting on page 46, through Section 13, and to Figure 6 on page 25, through Figure 9. A detected address parity
error on any read transaction results in a target abort; refer to Figure 11 on page 28. Address parity errors on write
transactions are still posted to the PCI core interface, but are discarded.
For burst transactions to the register space, the application side of the PCI core interface operates faster than the
PCI bus, so the PCI core interface FIFOs will never get full. PCI_TRDY# remains asserted for all valid data phases
applied.
4.1.3 Connection Memory Space Target Access
The T8110 connection memory is always immediately available for access (via dedicated access times assigned
for PCI bus target transactions). Read and write bursting is allowed to this region. For more details on connection
memory programming, see Section 14.1 on page 136, and Figure 6 through Figure 9. A detected address parity
error on any read transaction results in a target abort; refer to Figure 11. Address parity errors on write transactions
are still posted to the PCI core interface, but are discarded.
For burst transactions to the connection memory space, the application side of the PCI core interface operates
slightly slower than the PCI bus, so the PCI core interface FIFOs may get full. In this case, PCI_TRDY# gets deas-
serted until the application side catches up.
4.1.4 Data Memory Space Target Access
The T8110 data memory is not guaranteed to be immediately available for access. Access to data memory is prior-
itized for standard H-bus/L-bus switching and packet payload switching, with PCI target access allowed as the low-
est priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the data
memory. Upon reception of a PCI read or write request, if the data memory is immediately available, the transac-
tion is completed as normal single-cycle access; refer to Figure 6 and Figure 7. If the data memory is not available
at the time of the request, any write cycle is posted and any read cycle becomes a delayed read. A detected
address parity error on any read transaction results in a target abort (refer to Figure 11 on page 28). Address parity
errors on write transactions are still posted to the PCI core interface, but are discarded.
4.1.4.1 Posted Write Transaction
Only one posted write to the data memory may be queued at a time; refer to Figure 6 for more details. The user
must
monitor a status bit (register status 8, bit 0; refer to Section 6.2.7) to determine whether a posted write is
already queued before attempting more writes. Subsequent posted write attempts to the data memory while a
queued posted write has not completed result in an error condition, and both writes (the queued one and the sub-
sequent one) are ignored. Error is reported at register status 7, bit 0 (refer to Section 6.2.5 on page 59). Subse-
quent read attempts from the data memory while a posted write is queued result in a target RETRY; please refer to
Figure 10.
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