
96
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
8 Frame Group and FG I/O
(continued)
8.4.1 Frame Group 8 kHz Reference Generation
Any of the T8110 FG signals may be used as programmable 8 kHz frame reference outputs. There are two sets of
control required, an offset delay from internal frame center, and pulse shaping.
The offset delay is provided via the FGx upper/lower start address registers. The delay is relative to the T8110
internal frame center, and the 12 bits used allow for 4096 different offsets, in increments of one 32.768 MHz clock
period (30.5 ns).
Pulse shaping is controlled via the FGx width and FGx rate registers. Pulses may be programmed to be active-high
or active-low. Pulse width can be either 1-bit, 2-bit, 4-bit, 1-byte or 2-byte wide (relative to the rate setting*), with
allowable rate settings of 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz.
*Pulse widths are bit times or multiples of bit times, for each applicable rate:
RATE
BIT TIME
2.048 Mbits/s
488 ns
4.096 Mbits/s
244 ns
8.192 Mbits/s
122 ns
16.384 Mbits/s
61 ns
Notes:
Frame group signals shown with offset = 0 (default). At offset = 0, the pulse starts at frame center.
Nonzero offsets denote 32.768 MHz period increments (30.5 ns) from frame center. There are up to 4096 increments within an 8 kHz frame
period. Offsets may be programmed in the range from 0—4095.
Frame group signals are shown as active high pulses (default)—they may be programmed as active-low pulses.
Diagram shows frame group pulse widths relative to bit-clock rate and time-slot width. This is applicable for any of the four frame group data
rates (2 Mbits/s, 4 Mbits/s, 8 Mbits/s, or 16 Mbits/s).
Figure 27. Frame Group 8 kHz Reference Timing
4
3
2
1
0
31, 63, 127 or 255
bitclock rate
(2, 4, 8, or
16MHz)
timeslot
Frame
Center
T8110 internal
frame
FG(x),
1-bit width,
offset = 0
FG(x),
2-bit width,
offset = 0
FG(x),
1-byte width,
offset = 0
FG(x),
2-byte width,
offset = 0
FG(x),
4-bit width,
offset = 0