
Agere Systems Inc.
201
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
JCCOB
JCDEB
JCDOB
JCEEB
JCEOB
JCFEB
JCFOB
JCOSR
JCWSR
JF0EB
JF0OB
JF1EB
JF1OB
JF2EB
JF2OB
JF3EB
JF3OB
JF4EB
JF4OB
JF5EB
JF5OB
JF6EB
JF6OB
JF7EB
JF7OB
JG0EB
JG0OB
JG1EB
JG1OB
JG2EB
JG2OB
JG3EB
JG3OB
JG4EB
JG4OB
JG5EB
JG5OB
JG6EB
JG6OB
JG7EB
JG7OB
Interrupt pending CLKERR C
Interrupt from CLKERR D
Interrupt pending CLKERR D
Interrupt from CLKERR E
Interrupt pending CLKERR E
Interrupt from CLKERR F
Interrupt pending CLKERR F
Interrupt CLKERR output mode
Interrupt CLKERR pulse width
Interrupt from FGIO 0
Interrupt pending FGIO 0
Interrupt from FGIO 1
Interrupt pending FGIO 1
Interrupt from FGIO 2
Interrupt pending FGIO 2
Interrupt from FGIO 3
Interrupt pending FGIO 3
Interrupt from FGIO 4
Interrupt pending FGIO 4
Interrupt from FGIO 5
Interrupt pending FGIO 5
Interrupt from FGIO 6
Interrupt pending FGIO 6
Interrupt from FGIO 7
Interrupt pending FGIO 7
Interrupt from GPIO 0
Interrupt pending GPIO 0
Interrupt from GPIO 1
Interrupt pending GPIO 1
Interrupt from GPIO 2
Interrupt pending GPIO 2
Interrupt from GPIO 3
Interrupt pending GPIO 3
Interrupt from GPIO 4
Interrupt pending GPIO 4
Interrupt from GPIO 5
Interrupt pending GPIO 5
Interrupt from GPIO 6
Interrupt pending GPIO 6
Interrupt from GPIO 7
Interrupt pending GPIO 7
Output
Enable
Output
Enable
Output
Enable
Output
Select
Select
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
Enable
Output
0x0060D
0x0060F
0x0060D
0x0060F
0x0060D
0x0060F
0x0060D
0x00613
0x00617
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00601
0x00600
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
0x00605
0x00604
4
5
5
6
6
7
7
—
—
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Table 133. Mnemonic Summary, Sorted by Name
(continued)
Mnemonic
Description
Type
Register
Bit Position