
210
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
GT4EB
GT5EB
GT6EB
GT7EB
GTPSR
SCMLR
SCLSB
FRMSB
SCMSB
SCULP
FB1SB
FB2SB
VCMEB
MBIEB
PDTSB
EBOLR
IEXLP
ISYLP
ICKLP
ICDSP
IASLR
CFLLR
CFHLN
CFSEN
CKMSR
CKMDR
P1ISR
P1RSR
N1SSB
N1DSB
N2SSB
N2DSB
ICMSB
CKRDR
P2RSR
LRISR
D1ISR
D1RSR
IR0SB
IR1SB
IR2SB
GP4 test-point
GP5 test-point
GP6 test-point
GP7 test-point
GP test-point MUX
Diagnostic, state counter mode low
Diagnostic, state counter mode EN
Diagnostic, /FR_COMP input
Diagnostic, state counter carry
Diagnostic, state counter mode high
APLL1 feedback reset
APLL2 feedback reset
Diagnostic, VC microprocessor access
Diagnostic, MB microprocessor access
Diagnostic, PCI discard timer
Diagnostic, external buffer retry
Diagnostic, interrupt control EXTERR
Diagnostic, interrupt control SYSERR
Diagnostic, interrupt control CLKERR
Diagnostic, interrupt control mode
Diagnostic, SYSERR assertion
Diagnostic sync-to-frame low
Diagnostic sync-to-frame high
Diagnostic sync-to-frame EN
Clock main
Clock main
APLL1 input
APLL1 rate
NR1 selector inversion
NR1 divider inversion
NR2 selector inversion
NR2 divider inversion
Invert clock main
Clock resource
APLL2 rate
Local reference input
DPLL1 input
DPLL1 rate
Invert local reference 0
Invert local reference 1
Invert local reference 2
Enable
Enable
Enable
Enable
Select
Load
Select
Select
Select
Load
Select
Select
Enable
Enable
Select
Load
Load
Load
Load
Select
Load
Load
Load
Enable
Select
Divide
Select
Select
Select
Select
Select
Select
Select
Divide
Select
Select
Select
Select
Select
Select
Select
0x00142
0x00142
0x00142
0x00142
0x00143
0x00144
0x00145
0x00145
0x00145
0x00145
0x00146
0x00146
0x00146
0x00146
0x00146
0x00147
0x00148
0x00148
0x00148
0x00148
0x00149
0x0014A
0x0014B
0x0014B
0x00200
0x00201
0x00202
0x00203
0x00204
0x00204
0x00204
0x00204
0x00204
0x00205
0x00207
0x00208
0x0020A
0x0020B
0x0020C
0x0020C
0x0020C
4
5
6
7
—
—
3
4
5
2:0
1
2
3
4
5
—
1:0
3:2
5:4
7:6
—
—
L
U
—
—
—
—
0
1
2
3
4
—
—
—
—
—
0
1
2
Table 134. Mnemonic Summary, Sorted by Register
(continued)
Mnemonic
Description
Type
Register
Bit Position