
Agere Systems Inc.
205
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
Appendix B. Register Bit Field Mnemonic Summary
(continued)
R7WLR
S2FEB
S2LOB
S2TOB
S2WEB
SCFEB
SCLOB
SCLSB
SCMLR
SCMSB
SCRSR
SCTOB
SCULP
SCWEB
SRBEB
SRESR
TCOSR
VCEON
VCMEB
VCOOB
VCPOB
VCSOB
VCSSR
VCTOB
VEROR
VPPOB
VSPOB
W0HLR
W0SLR
W0WLR
W1HLR
W1SLR
W1WLR
W2HLR
W2SLR
W2WLR
W3HLR
W3SLR
W3WLR
W4HLR
W4SLR
MB_CS7 read cycle width
/SCLKx2 fallback trigger
/SCLKx2 latched error
/SCLKx2 transient error
/SCLKx2 watchdog
SCLK fallback trigger
SCLK latched error
Diag state counter mode EN
Diag state counter mode low
Diag state counter carry
SCLK/SCLKx2 rate
SCLK transient error
Diag state counter mode high
SCLK watchdog
Soft reset of back end
Soft reset
T clock output
VC enable status
Diag VC microprocessor access
VC memory overflow warning
VC memory PCI error
VC memory PCI queue
VC start command reg
VC memory PCI timer
Version ID register
VC pause pending
VC start pending
MB_CS0 write cycle hold
MB_CS0 write cycle setup
MB_CS0 write cycle width
MB_CS1 write cycle hold
MB_CS1 write cycle setup
MB_CS1 write cycle width
MB_CS2 write cycle hold
MB_CS2 write cycle setup
MB_CS2 write cycle width
MB_CS3 write cycle hold
MB_CS3 write cycle setup
MB_CS3 write cycle width
MB_CS4 write cycle hold
MB_CS4 write cycle setup
Load
Enable
Output
Output
Enable
Enable
Output
Select
Load
Select
Select
Output
Load
Enable
Enable
Select
Select
Output
Enable
Output
Output
Output
Select
Output
Output
Output
Output
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
0x00771
0x0010A
0x00122
0x00120
0x0010E
0x0010A
0x00122
0x00145
0x00144
0x00145
0X00227
0x00120
0x00145
0x0010E
0x00101
0x00100
0x00226
0x0012D
0x00146
0x00126
0x00127
0x0012C
0x00104
0x00127
0x00128
0x0012D
0x0012D
0x00706
0x00704
0x00705
0x00716
0x00714
0x00715
0x00726
0x00724
0x00725
0x00736
0x00734
0x00735
0x00746
0x00744
—
7
7
7
7
6
6
3
—
5
—
6
2:0
6
0
—
—
L
3
1
1
1
—
4
—
5
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 133. Mnemonic Summary, Sorted by Name
(continued)
Mnemonic
Description
Type
Register
Bit Position