
50
Agere Systems Inc.
Data Sheet
May 2001
and Packet Payload Engine
Ambassador T8110 PCI-Based H.100/H.110 Switch
6 Operating Control and Status
(continued)
6.1.5 Phase Alignment Select Register
The phase alignment select register selects the phase alignment configuration. For more details, see Section
7.4.5.1 on page 80. The T8110 internally generates an 8 kHz frame reference. Shown below are three configura-
tions to control phase alignment between this internally generated frame reference and a selected incoming frame
reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]).
n
Disable alignment, no realignment of unaligned frames
n
Snap alignment, immediate realignment of unaligned frames
n
Slide alignment, gradual realignment of unaligned frames
6.1.6 Fallback Control Register
The fallback control register allows user control over the active and inactive clock register sets. For more details,
see Section 7.7.1 on page 82. Writes to the fallback control register trigger the corresponding action, and the set
bit(s) are automatically cleared. The four commands are shown below:
n
GO_CLOCKS. At initialization, the clock register Y set is active, the X set is inactive, and access is enabled to
the X set. The GO_CLOCKS command transitions the Y set to inactive and the X set to active. This command
can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference
(synchronized to frame).
n
CLEAR_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets
after a fallback event has occurred. This command can either be performed immediately upon issue or can wait
to be performed until the next 8 kHz frame reference (synchronized to frame).
n
FORCE_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets
by creating a fallback event. This command can either be performed immediately upon issue or can wait to be
performed until the next 8 kHz frame reference (synchronized to frame).
n
COPY ACTIVE TO INACTIVE SET. Copies all register values in the current active clock register set to the inac-
tive clock register set. This command is performed immediately upon issue.
Table 27. Phase Alignment Select Register
Byte
Address
Name
Bit(s) Mnemonic
Value
Function
0x00107
Phase Alignment Select
7:0
PAFSR
0000 0000
0000 0001
0000 0010
Phase alignment is disabled (default).
Enable snap alignment.
Enable slide alignment.