TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
216
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 263. M13_DS1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Status
Registers (RO)
Table 264. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)
Table 265. M13_RDL_STATUS, Receive Data-Link Status (RO)
Address
Bit
Name
Function
Reset
Default
0x00
0
0x1004D
15:8
7
RSVD
Reserved.
When an FEAC loopback activate codeword for
DS3 is received four consecutive times, the bit is
set high. The bit is cleared when a loopback deac-
tivate codeword is received four consecutive
times.
Reserved.
Reserved.
M13_DS3_FLB_DET
6:4
15:8
RSVD
RSVD
000
0x00
0x1004E
0x1004F
0x10050
0x1004D
15:8
15:8
3:0
RSVD
RSVD
Reserved.
Reserved.
When an FEAC loopback activate codeword for
DS1 is received four consecutive times, the
appropriate bit(s) is set high. The bit(s) is cleared
when a loopback deactivate codeword for that
channel(s) is received four consecutive times.
0x00
0x00
0x0
0x1004E
0x1004F
0x10050
7:0
7:0
7:0
M13_DS1_FEAC_LB_DET[28:25]
M13_DS1_FEAC_LB_DET[24:17]
M13_DS1_FEAC_LB_DET[16:9]
M13_DS1_FEAC_LB_DET[8:1]
0x00
0x00
0x00
Address
Bit
Name
Function
Reset
Default
000000
0000
0x3F
0x10051
15:6
RSVD
Reserved.
5:0
M13_RFEAC_CODE[5:0]
M13_RFEAC_CODE[5:0] Bits.
When the same codeword
is received through the FEAC channel four consecutive
times, M13 will set M13_RFEAC_CODE[5:0] =
x5x4x3x2x1x0, where the received FEAC codeword is
0x5x4x3x2x1x0 0 11111111, and it is received right to left.
Address
Bit
Name
Function
Reset
Default
0x000
0
0x10052 15:5
RSVD
Reserved
.
This bit is high if the closing flag or an abort byte has been
received.
This bit is high if the frame was ended with an abort byte
rather than a closing flag.
M13_RDL_NOT_BYTE This bit is set if the number of bits in the frame (after removal
of stuffed zeros) is not a multiple of 8.
M13_RDL_OVFL
This bit is set if at least 1 byte of the frame was overwritten by
a byte from a succeeding frame before being read.
M13_RDL_FCS_ERR
This bit is set if the CRC-16 check fails and
M13_RDL_FCS = 1 (
Table 299 on page 227
).
4
M13_RDL_FLAG
3
M13_RDL_ABORT
0
2
0
1
0
0
0