TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
292
Agere Systems Inc.
12 28-Channel Framer Registers
(continued)
The register in
Table 407
provides a status indication of functional elements (FE) exchanged between the access
digital section and the exchange termination (ET), as defined in ETS 300 233, Section 9.3 and Table 3 and Table
4.
Table 407. FRM_PMLR14, Performance Monitor Link Register 14 (COR)
* See
Table 393 on page 279
for values of L and P.
Table 408. FRM_PMLR15, Performance Monitor Link Register 15 (COR)
* See
Table 393 on page 279
for values of L and P.
Table 409. FRM_PMLR16, Performance Monitor Link Register 16 (COR)
* See
Table 393 on page 279
for values of L and P.
Table 410. FRM_PMLR17, Performance Monitor Link Register 17 (COR)
* See
Table 393 on page 279
for values of L and P.
Table 411. FRM_PMLR18, Performance Monitor Link Register 18 (COR)
* See
Table 393 on page 279
for values of L and P.
Address
*
Bit
Name
Function
(A, Sa5, Sa6[1:4], E)
Reset
Default
0x000
0
0
0
0
0
0
0
0
0
0x8LP8D
15:9
8
7
6
5
4
3
2
1
0
RSVD
FRM_FE_Y
FRM_FE_X
FRM_FE_W
CRC Error Reported from TE.
(x, 1, 0001, x.)
FRM_FE_V
CRC Error Information from ET.
(x, 0, 0000, 0.)
FRM_FE_U
CRC Error Report from NT1 Line Side.
(x, 1, xxxx, 0.)
FRM_FE_T
Loopback Release Command.
(x, 0, 0000, x.)
FRM_FE_S
Loopback Acknowledge.
(1, 0, xxxx, x.)
FRM_FE_R
Loopback 2 Command.
(1, 0, 1010, x.)
FRM_FE_Q
Loopback 1 Command.
(1, 0, 1111, x.)
Reserved.
Must write to 0.
Simultaneous Occurrence of FE_W and FE_X.
(x, 1, 0011, x.)
CRC Error Detected at T Reference Point of NT1.
(x, 1, 0010, x.)
Address
*
Bit
Name
Function
Reset
Default
0x0000
0x8LP8E
15:0
FRM_ESC[15:0]
Errored Second Counter.
This register contains the 16-bit
count of errored seconds.
Address
*
Bit
Name
Function
Reset
Default
0x0000
0x8LP8F
15:0
FRM_BESC[15:0]
Bursts Errored Second Counter.
This register contains the
16-bit count of bursty errored seconds.
Address
*
Bit
Name
Function
Reset
Default
0x0000
0x8LP90
15:0
FRM_SESC[15:0]
Severely Errored Second Counter.
This register contains the
16-bit count of severely errored seconds.
Address
*
Bit
Name
Function
Reset
Default
0x00
0x00
0x8LP91
15:8
7:0
RSVD
Reserved.
Must write to 0.
FRM_RBOM[7:0]
Received Bit-Oriented Message (0xxxxxx0).
Note that only
storing the 8 bits that contain actual data, the first eight ones are
not stored.