Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
93
Agere Systems Inc.
8 TMUX Registers
(continued)
Note:
In
Table 98
, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 98. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Note:
When state bits are set in
Table 99
, the corresponding function has occurred.
Table 99. TMUX_TX_STATE, State Parameters (RO)
Note:
When state bits are set in
Table 100
, the corresponding function has occurred.
Table 100. TMUX_RPS_STATE, State and Value Parameters (RO)
Address
Bit
Name
Function
Reset
Default
0x000
1
0x40011
15:8
7
RSVD
Reserved.
Receive High-Speed Signal Fail BER Algorithm
APSINT Mask.
See
Table 92 on page 81
for descrip-
tion.
Receive High-Speed Signal Degrade BER Algo-
rithm APSINT Mask.
See
Table 92
for description.
TMUX_RHSSF_APSM
6
TMUX_RHSSD_APSM
1
5
TMUX_RAPSMON_APSM
Receive APS Monitor APSINT Mask.
See
Table 93
for description.
TMUX_RLAISMON_APSM
Receive Line AIS Monitor APSINT Mask.
See
Table 92
for description.
TMUX_RHSLOS_APSM
Receive High-Speed Loss of Signal APSINT Mask.
See
Table 92
for description.
TMUX_RHSLOF_APSM
Receive High-Speed Loss of Frame APSINT Mask.
See
Table 92
for description.
TMUX_RHSOOF_APSM
Receive High-Speed Out of Frame APSINT Mask.
See
Table 92
for description.
TMUX_RHSILOC_APSM
Receive High-Speed Loss of Input Clock APSINT
Mask.
See
Table 92
for description.
1
4
1
3
1
2
1
1
1
0
1
Address
Bit
Name
Function
Reset
Default
0x000
0
0x40012
15:2
1
RSVD
Reserved.
TMUX_THSILOF
Transmit High-Speed Input Loss of Frame State.
See
Table 90 on page 80
for description.
TMUX_THSILOC
Transmit High-Speed Input Loss of Clock State.
See
Table 90
for description.
0
0
Address
Bit
Name
Function
Reset
Default
0x000
0
0x40013
15:6
5
RSVD
Reserved.
Receive Protection High-Speed Loss of Frame State.
See
Table 91 on page 80
for description.
TMUX_RPSOOF
Receive Protection High-Speed Out of Frame State.
See
Table 91
for description.
TMUX_RPSILOC
Receive Protection High-Speed Loss of Input Clock State.
See
Table 91
for description.
RSVD
Reserved.
TMUX_RPSLOF
4
0
3
0
2:0
000