TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
416
Agere Systems Inc.
18 SPE Mapper Functional Description
(continued)
I
The pointer interpreter transitions into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (
Table 159 on page 141
)), if 8 of the 10 I and
D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions
into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on
the incoming H1 and H2 bytes, the pointer interpreter transitions into the DEC state.
I
The pointer interpreter transitions out of the DEC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into
the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the DEC state into the AIS-TU3 state.
— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the
DEC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state.
I
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from
TMUX), bit SPE_RLOP = 1 (
Table 158 on page 140
), or bit SPE_RAIS = 1 (
Table 158
).
— Latched counts, SPE_RPTR_INC[10:0] (
Table 171 on page 151
) and SPE_RPTR_DEC[10:0] (
Table 171
), will
be updated coincident with the end of a performance monitor interval.
— The internal counters will reset to 0x00 coincident with the end of a performance monitor interval.
— If SMPR_SAT_ROLLOVER = 1 (
Table 77 on page 70
), the internal running counts will hold at their maximum
value. Otherwise, the counts will roll over.
— However, increment and decrement event indications should be ignored during LOP state.
I
LOP-TU3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detected and reported to the microprocessor.
Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper
to the VT mapper. Any change in state of SPE_RLOP (
Table 158 on page 140
) or SPE_RAIS (
Table 158
) will be
reported to the microprocessor via SPE_RLOPD (
Table 156 on page 136
) and SPE_RAISD (
Table 156
). Unless
the appropriate mask bit is set (SPE_RLOPM/SPE_RAISM (
Table 157 on page 138
)), SPE_RLOPD = 1 or
SPE_RAISD = 1 will generate an interrupt.
I
Table 171 on page 151
).
18.14 SPE Mapper Receive Direction Requirements
All monitoring functions supported by the SPE mapper in the receive direction are summarized here:
I
Loss of CLOCK and loss of sync monitors
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J2 monitor
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B3 BIP-8 check
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C2 signal label monitor
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F2 monitor
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F3 monitor
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N1 monitor
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K3 monitor
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AIS-P and RDI-P detect
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REI-P detect
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Signal degrade BER algorithm
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Signal fail BER algorithm
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Path overhead access channel (POAC) drop
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Insertion of AIS-P