64
Agere Systems Inc.
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
Register Description
7 Microprocessor Interface and Global Control and Status Registers
Table of Contents
Contents
Page
7 Microprocessor Interface and Global Control and Status Registers ................................................................ 64
7.1 Supermapper Global Control and Status Registers.....................................................................................65
7.2 Microprocessor Interface Register Map .......................................................................................................75
Tables
Page
Table 67. SMPR_VCR, Supermapper Version Control Register (RO) ....................................................................65
Table 68. SMPR_SYMR[4], Supermapper Symbol Register4 SMPR (RO).............................................................65
Table 69. SMPR_SYMR[3], Supermapper Symbol Register3 (RO)........................................................................65
Table 70. SMPR_SYMR[2], Supermapper Symbol Register2 (RO)........................................................................65
Table 71. SMPR_SYMR[1], Supermapper Symbol Register1 (RO)........................................................................65
Table 72. SMPR_SYMR[0], Supermapper Symbol Register0 (RO)........................................................................65
Table 73. SMPR_ISR, Supermapper Interrupt Status Register (RO)......................................................................66
Table 74. SMPR_IMR, Supermapper Interrupt Mask Register (RW) ......................................................................67
Table 75. SMPR_GTR, Global Trigger Register (RW).............................................................................................68
Table 76. SMPR_MSRR, Block Software Reset Register (RW)..............................................................................68
Table 77. SMPR_GCR, Global Control Register (RW)............................................................................................70
Table 78. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW)..................................................................71
Table 79. SMPR_FCR, Framer Control Register (RW) ...........................................................................................71
Table 80. SMPR_CLCR, CDR, and LVDS Control Register (RW)...........................................................................72
Table 81. SMPR_CPCR, Clock and Power Control Register (RW).........................................................................73
Table 82. SMPR_PMRCHR, PM Reset Count High Register (RW) ........................................................................73
Table 83. SMPR_PMRCLR, PM Reset Count Low Register (RW)..........................................................................74
Table 84. SMPR_TX_LINE_EN1.............................................................................................................................74
Table 85. SMPR_SR, Scratch Register (RW)..........................................................................................................74
Table 86. Microprocessor Interface Register Map...................................................................................................75