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參數(shù)資料
| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 10/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Table of Contents
(continued)
Contents
Page
8
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
15.3.4 Transfer End ...............................................................................................................................211
15.3.4.1 Master Operation ...........................................................................................................211
15.3.4.2 Slave Operation .............................................................................................................211
15.3.5 Interrupt Generation ....................................................................................................................212
15.3.6 Status Flags and Error Conditions ..............................................................................................212
15.3.6.1 SDONE ..........................................................................................................................212
15.3.6.2 WCOLL Flag ..................................................................................................................212
15.3.6.3 MODF ............................................................................................................................212
15.3.6.4 RD_ORUN .....................................................................................................................213
15.3.7 SSI Transfer Abort .......................................................................................................................213
15.3.8 SSNEN Control Register Bit ........................................................................................................214
16 Parallel Peripheral Interface (PPI) .................................................................................................................215
16.1 PPI Operation ........................................................................................................................................215
16.1.1 PPI Pin Configuration on Reset ...................................................................................................216
16.1.2 Procedure for Writing to an Output Pin .......................................................................................216
16.1.3 Procedure for Reading from an Input Pin ....................................................................................216
16.1.3.1 Additional Read/Write Notes .........................................................................................216
16.1.4 PPI Port Interrupts .......................................................................................................................217
16.2 PPI Registers .........................................................................................................................................218
16.2.1 PPI Data Direction Register ........................................................................................................218
16.3 PPI Port Data Register ...........................................................................................................................218
16.3.1 PPI Interrupt Enable Register ......................................................................................................219
16.3.2 PPI Port Sense Register .............................................................................................................219
16.3.3 PPI Port Polarity Register ............................................................................................................220
16.3.4 PPI Pull-Up Enable Register .......................................................................................................221
16.3.5 PPI Port Data Clear Register ......................................................................................................221
16.3.6 PPI Port Data Set Register ..........................................................................................................221
16.4 Summary of Programming Modes .........................................................................................................222
17 Key and Lamp Controller (KLC) .....................................................................................................................223
17.1 KLC Operation .......................................................................................................................................224
17.1.1 LED Drive Matrix Operation ........................................................................................................224
17.1.2 Key Scan Matrix Operation .........................................................................................................224
17.1.3 KLC Interrupts .............................................................................................................................226
17.1.4 Timing and Reset ........................................................................................................................226
17.2 KLC LED Drive and Key Scan Matrix Pins ............................................................................................226
17.3 KLC Register ..........................................................................................................................................227
17.3.1 Lamp Rate Registers ...................................................................................................................227
17.3.2 KLC Noscan Control Register .....................................................................................................228
17.3.3 Key Scan Status Register ...........................................................................................................229
17.3.4 KLC Interrupt Register .................................................................................................................230
17.3.5 KLC Interrupt Enable Register ....................................................................................................230
18 JTAG/Boundary Scan ....................................................................................................................................231
18.1 Debug Support .......................................................................................................................................231
18.2 The Principle of Boundary Scan Architecture ........................................................................................231
18.2.1 Instruction Register .....................................................................................................................233
18.3 Boundary Scan Register ........................................................................................................................234
19 Electrical Specifications .................................................................................................................................242
19.1 Absolute Maximum Ratings ...................................................................................................................242
19.2 Handling Precautions .............................................................................................................................242
19.3 Crystal Specifications .............................................................................................................................242
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