
28
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
3 Overview
(continued)
3.1
ARM
940
T and
AMBA
Bridge
The
ARM
940T is a full 32-bit microprocessor with integrated instruction and data cache. This processor core con-
tains many high-performance features. The
AMBA
APB bridge is a flexible interface between the high-performance
AMBA
ASB bus and the
AMBA
APB bus. Documentation for the
ARM
940T and these buses can be found at the
website:
http://www.arm.com
3.2 IPT_
ARM
Memory and I/O Map
The buses, along with an external memory controller provide the logic and decoding to access and support the
memories and peripherals on and off the IPT_
ARM
. The IPT_
ARM
processor memory and I/O map is shown
below.
.
Table 2.
ARM
Processor Memory and I/O Map
Description
Address
This range is shared between ROM (FLASH), external SDRAM, FLASH_CS, CS1,
CS2, CS3, and internal SRAM with programmable base addresses.
Reserved for
ARM
940T processor.
Reserved.
Reset/clock controller register map
(see Table 4 on page 35)
;
includes version ID
register.
Programmable interrupt controller register map
(see Table 25 on page 50)
.
DMA controller register map
(see Table 35 on page 61)
.
EMI FLASH register map
(see Table 57 on page 84)
.
SSI register map
(see Table 181 on page 203)
.
Timer controller register map
(see Table 46 on page 73)
.
PPI parallel I/O controller register map
(see Table 188 on page 218)
.
USB operational register map
(see Table 144 on page 163)
.
IrDA_ACC communications controller register map
(see Table 169 on page 189)
.
UART_ACC communications controller register map
(see Table 169 on page 189)
.
Reserved.
RTC control registers
(see Table 17 on page 43)
.
Key and lamp controller registers
(see Table 202 on page 229)
.
Reserved.
ARM
processor memory and I/O map
(see Table 72 on page 96)
.
MAC register map
(see Table 77 on page 105)
.
Reserved.
Repeater slice register map
(see Table 113 on page 133)
.
Reserved.
ARM
2DSP data buffer (512x32)
ARM
write only
(see Table 72 on page 96)
.
Reserved.
DSP2
ARM
data buffer (512x32) read-only
(see Table 72 on page 96)
.
Reserved.
0x0000 0000:0xBFFF FFFF
0xC000 0000:0xCFFF FFFF
0xD000 0000:0xDFFF FFFF
0xE000 0000:0xE000 0FFF
0xE000 1000:0xE000 1FFF
0xE000 2000:0xE000 2FFF
0xE000 3000:0xE000 3FFF
0xE000 4000:0xE000 4FFF
0xE000 5000:0xE000 5FFF
0xE000 6000:0xE000 6FFF
0xE000 7000:0xE000 7FFF
0xE000 8000:0xE000 8FFF
0xE000 9000:0xE000 9FFF
0xE000 A000:0xE000 AFFF
0xE000 C000:0xE000 CFFF
0xE000 D100:0xE000 DFFF
0xE000 E000:0xE000 EFFF
0xE000 F000:0xE000 FFFF
0xE001 0000:0xE001 0FFF
0xE001 1000:0xE001 1FFF
0xE001 2000:0xE001 2FFF
0xE001 3000:0xE003 FFFF
0xE004 0000:0xE004 07FF
0xE004 0800:0xE005 FFFF
0xE006 0000:0xE006 07FF
0xE008 0000:0xFFFF FFFF